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    NFC device configuration after device power up
    673.
    发明授权
    NFC device configuration after device power up 有权

    公开(公告)号：US09615196B2

    公开(公告)日：2017-04-04

    申请号：US14640138

    申请日：2015-03-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Constantin Socol ,  Daniel Orsatti

    IPC: H04B5/00 ,  H04W4/00

    CPC classification number: H04W4/008 ,  H04W4/80

    Abstract: A NFC tag includes an NFC controller, with a secure element coupled to the NFC controller. The secure element is to send first configuration data to the NFC controller and not second configuration data. The first configuration data comprises data to be used by the NFC controller to generate responses to initial polling and anti-collision commands from an external NFC device and not data to be used by the NFC controller in processing a command from the external NFC device involving the use of an upper layer protocol. The second configuration data comprises data to be used by the NFC controller in processing a command involving the use of an upper layer protocol from the external NFC device.

    System and method for improving memory performance and identifying weak bits
    675.
    发明授权
    System and method for improving memory performance and identifying weak bits 有权
    用于提高记忆性能和识别弱位的系统和方法

    公开(公告)号：US09543044B2

    公开(公告)日：2017-01-10

    申请号：US14074341

    申请日：2013-11-07

    Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.R.L.

    Inventor： Abhishek Jain ,  Andrea Mario Veggetti ,  Amit Chhabra

    IPC: G11C29/48 ,  G06F1/08 ,  G11C29/24 ,  G11C29/52 ,  G11C29/54

    CPC classification number: G11C29/48 ,  G06F1/08 ,  G06F11/00 ,  G11C29/24 ,  G11C29/52

    Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

    Abstract translation: 根据本文描述的实施例，用于测试存储器的方法包括在存储器处接收地址和起始信号，并且响应于起始信号在测试电路产生第一检测器脉冲。 第一检测器脉冲具有前沿和后沿。 检测与地址相关联的位的数据转换。 该位是一个功能位。 该方法还包括通过确定在后沿之后是否发生数据转换来确定该位是否为弱位。

    ENHANCED AUGMENTED REALITY MULTIMEDIA SYSTEM
    676.
    发明申请
    ENHANCED AUGMENTED REALITY MULTIMEDIA SYSTEM 审中-公开
    增强现实的多媒体系统

    公开(公告)号：US20160379410A1

    公开(公告)日：2016-12-29

    申请号：US14750699

    申请日：2015-06-25

    Applicant: STMicroelectronics International N.V.

    Inventor： Amit Sharma ,  Gaurav Jairath ,  Paramanand Singh ,  Amit Kumar Srivastava

    IPC: G06T19/00 ,  G06F17/30 ,  G06T7/00 ,  G06T11/00

    CPC classification number: G06T19/006 ,  G06F16/44 ,  G06F16/487 ,  G06T11/60 ,  H04N21/41407 ,  H04N21/4316 ,  H04N21/4722 ,  H04N21/4728

    Abstract: A method for operating an augmented reality system includes acquiring video data from a camera sensor or video file, and identifying at least one region of interest within the video data. Augmented reality data is generated for the region of interest without receiving user input, with the augmented reality data being contextually related to the region of interest. The video data may be displayed with the augmented reality data superimposed thereupon in real time as the video data is acquired from the camera sensor or video file. The video data and the augmented reality data are stored in a non-conflated fashion. The video data may be displayed with updated AR content acquired for stored AR metadata during later playback. The method therefore allows the storage of AR ROI's and data from any suitable sensor as metadata, so that later retrieval is possible in the absence of additional processing.

    Abstract translation: 用于操作增强现实系统的方法包括从相机传感器或视频文件获取视频数据，以及识别视频数据内的至少一个感兴趣区域。 为感兴趣的区域生成增强的现实数据，而不接收用户输入，增强的现实数据与感兴趣的区域上下文相关。 当从摄像机传感器或视频文件获取视频数据时，视频数据可以与其上叠加的增强现实数据实时显示。 视频数据和增强现实数据以非混合方式存储。 视频数据可以在随后的再现期间以存储的AR元数据获取的更新的AR内容显示。 因此，该方法允许将AR ROI和来自任何合适的传感器的数据存储为元数据，使得在没有附加处理的情况下稍后检索是可能的。

    Integrated device comprising a matrix of OLED active pixels with improved dynamic range
    677.
    发明授权
    Integrated device comprising a matrix of OLED active pixels with improved dynamic range 有权
    包括具有改进的动态范围的OLED有源像素矩阵的集成器件

    公开(公告)号：US09521723B2

    公开(公告)日：2016-12-13

    申请号：US14723942

    申请日：2015-05-28

    Applicant: STMicroelectronics International N.V.

    Inventor： Jerome Nebon ,  Christophe Forel

    IPC: H01L27/32 ,  H05B33/08 ,  G09G3/32

    CPC classification number: H05B33/0896 ,  G09G3/3233 ,  G09G2300/0814 ,  G09G2320/0247 ,  G09G2320/045

    Abstract: An integrated device includes a semiconducting substrate having a matrix of active pixels formed therein. Each active pixel includes an OLED diode, a first nMOS transistor having its source coupled to an anode of the OLED diode, and a refresh circuit coupled to a gate of the first nMOS transistor. The first nMOS transistor has its source and its substrate coupled together. The first nMOS transistor is situated in and on a first part of the semiconductor substrate, and the refresh circuit is situated in and on a second part of the semiconductor substrate, with the first part and the second part being electrically insulated from one another.

    Abstract translation: 集成器件包括其中形成有有源像素的矩阵的半导体衬底。 每个有源像素包括OLED二极管，其源极耦合到OLED二极管的阳极的第一nMOS晶体管，以及耦合到第一nMOS晶体管的栅极的刷新电路。 第一个nMOS晶体管具有其源极及其衬底耦合在一起。 第一nMOS晶体管位于半导体衬底的第一部分中并且位于半导体衬底的第一部分上，并且刷新电路位于半导体衬底的第二部分中并位于半导体衬底的第二部分上，其中第一部分和第二部分彼此电绝缘。

    On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking
    679.
    发明授权
    On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking 有权
    使用片上时钟设计的ATPG故障的即时测试和调试逻辑

    公开(公告)号：US09482719B2

    公开(公告)日：2016-11-01

    申请号：US14152130

    申请日：2014-01-10

    Applicant: STMicroelectronics International N.V.

    Inventor： Danish Hasan Syed

    IPC: G06F11/00 ,  G01R31/317 ,  G01R31/3181

    CPC classification number: G01R31/31727 ,  G01R31/31705 ,  G01R31/31707 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31813

    Abstract: A semiconductor chip includes an OCC that receives an ATPG test pattern and generates clock pulses in response. An OCC test circuit detects clock pulses of the OCC circuit and provides debug data to test output configurable logic that also receives results from other circuits testing different DUT flip-flops. A clipping test circuit detects ATPG failures due to clipped clock pulses from the OCC by providing pulse-width sensitive flip-flop outputs to DUT I/Os. An IR drop test circuit detects if ATPG failures are due to IR-drop problems in certain flip-flops. A pulse bit manipulating circuit varies the test pattern provided to the OCC and OCC-generated clock pulses. A debug controller connected to test output configurable logic selects between results of the different tests for supply as an output test signal to be compared on-the-fly with expected pattern data on ATE and used to isolate errors on the chip.

    Abstract translation: 半导体芯片包括接收ATPG测试图案并产生响应的时钟脉冲的OCC。 OCC测试电路检测OCC电路的时钟脉冲，并提供调试数据以测试输出可配置逻辑，其也接收来自测试不同DUT触发器的其他电路的结果。 削波测试电路通过向DUT I / O提供脉冲宽度敏感的触发器输出来检测来自OCC的剪辑时钟脉冲的ATPG故障。 IR跌落测试电路检测ATPG故障是否由于某些触发器中的IR降低问题。 脉冲位操作电路改变提供给OCC和OCC产生的时钟脉冲的测试模式。 连接到测试输出可配置逻辑的调试控制器在不同测试结果之间选择供应作为输出测试信号，与ATE上的预期模式数据进行比较，并用于隔离芯片上的错误。

    Driver circuit including driver transistors with controlled body biasing
    680.
    发明授权
    Driver circuit including driver transistors with controlled body biasing 有权
    驱动电路包括具有受控体偏置的驱动晶体管

    公开(公告)号：US09473135B2

    公开(公告)日：2016-10-18

    申请号：US14500076

    申请日：2014-09-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Paras Garg ,  Rajesh Yadav ,  Saiyid Mohammad Irshad Rizvi ,  Ravinder Kumar

    IPC: H03K3/00 ,  H03K17/687 ,  H03K19/0185

    CPC classification number: H03K17/687 ,  H03K19/0185 ,  H03K2217/0018

    Abstract: A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad.

    Abstract translation: 驱动电路包括耦合在集成电路的第一电源节点和输出焊盘之间的第一驱动晶体管，以及耦合在第二电源节点和输出焊盘之间的第二驱动晶体管。 第一驱动晶体管和第二驱动晶体管由控制信号控制。 体偏置发生器电路被配置为将可变第一体偏置施加到第一晶体管，并将可变第二体偏置施加到第二晶体管。 可变的第一和第二体偏置作为控制信号和输出焊盘处的电压的函数产生。

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