公开(公告)号：US12239425B2

公开(公告)日：2025-03-04

申请号：US17373015

申请日：2021-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Woo Choi ,  Jae Min Kang ,  Seung Woo Noh ,  Sang Yun Park ,  Hye Rim Lim

IPC: A61B5/022 ,  A61B5/00 ,  A61B5/021 ,  A61B5/024

Abstract: An apparatus for estimating blood pressure is provided. According to one embodiment, the apparatus for estimating blood pressure may include: a first sensor configured to obtain a pulse wave signal of a green wavelength from an object when the object is in contact with the first sensor; a second sensor configured to measure an external force applied to the second sensor while the first sensor is obtaining the pulse wave signal; and a processor configured to obtain an oscillometric envelope based on a direct current (DC) component of the pulse wave signal of the green wavelength and the external force, and estimate the blood pressure using the oscillometric envelope.

公开(公告)号：US12239422B2

公开(公告)日：2025-03-04

申请号：US17349419

申请日：2021-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung Hoon Ko ,  Yong Joo Kwon ,  Seung Woo Noh ,  Hyun Seok Moon ,  Sung Mo Ahn ,  Kun Sun Eom ,  Jong Wook Lee ,  Tak Hyung Lee ,  Myoung Hoon Jung ,  Chang Mok Choi

IPC: A61B5/0205 ,  A61B5/00 ,  A61B5/1455 ,  A61B90/00

Abstract: An apparatus for estimating biological information may include a sensor configured to detect a first light signal and a second light signal from an object of a user and a processor configured to determine whether a condition for estimating biological information is satisfied based on the detected first light signal and estimate biological information based on the second light signal, wherein the sensor includes a force sensor configured to measure a force applied to the object when the object is in contact with a cover surface of the sensor.

公开(公告)号：US12239284B2

公开(公告)日：2025-03-04

申请号：US17289029

申请日：2019-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwan Lee ,  Yeongrok Lee ,  Hyunseok Hong

IPC: A47L9/04 ,  A47L9/00 ,  A47L9/28

Abstract: Provided is a cleaning device including a suction port; at least one sensor configured to sense at least one object; a driver configured to open or close the suction port; a memory storing at least one instruction; and a processor configured to execute the at least one instruction stored in the memory. The processor executes the at least one instruction to sense at least one object within an area to be cleaned by the cleaning device by controlling the at least one sensor, identify a relative location of the sensed at least one object with respect to the cleaning device, determine at least a partial area within an entire area of the suction port as an open/close target area, based on the identified relative location of the at least one object, and open or close the open/close target area by controlling the driver.

公开(公告)号：US20250072107A1

公开(公告)日：2025-02-27

申请号：US18944448

申请日：2024-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGIL PARK ,  JAE HYUN PARK ,  DAEWON HA ,  KYUMAN HWANG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.

公开(公告)号：US20250072098A1

公开(公告)日：2025-02-27

申请号：US18486884

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mehdi Saremi ,  Ming He ,  Aravindh Kumar ,  Muhammed Ahosan Ul Karim ,  Rebecca Park ,  Harsono Simka

IPC: H01L21/8238 ,  H01L29/08

Abstract: A method of manufacturing a three-dimensional field-effect transistor including an upper field-effect transistor stacked on a lower field-effect transistor. The method includes epitaxially growing source/drain regions of the lower field-effect effect transistor, growing a sacrificial layer on an upper surface of the source/drain regions, and epitaxially growing source/drain regions of the upper field-effect transistor on the sacrificial layer. The sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor. The method also includes selectively etching the sacrificial layer to form a gap between the source/drain regions of the lower field-effect transistor and the source/drain regions of the upper field-effect transistor, and depositing an oxide layer in the gap.

公开(公告)号：US20250072096A1

公开(公告)日：2025-02-27

申请号：US18606375

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Woong SHIM ,  Seong Heum CHOI ,  Do Sun LEE ,  Hyo Seok CHOI ,  Rak Hwan KIM ,  Chung Hwan SHIN

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method of fabricating a semiconductor device includes: forming an active pattern on a substrate, forming a source/drain pattern on the active pattern, forming a contact hole on the source/drain pattern, forming a contact barrier layer, which has an upper surface of a first height based on a bottom surface of the contact hole, in the contact hole, forming a passivation layer on the contact barrier layer in the contact hole, forming a mask layer on the passivation layer in the contact hole, removing an upper portion of the contact barrier layer so that an upper surface of the contact barrier layer has a second height lower than the first height, removing the passivation layer and the mask layer, and forming a contact filling layer, which covers the upper surface of the contact barrier layer and fills the contact hole, in the contact hole.

公开(公告)号：US20250072087A1

公开(公告)日：2025-02-27

申请号：US18583269

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook PARK ,  Sangmin KANG ,  Changwoo SEO ,  Suyoun SONG ,  Dain LEE

IPC: H01L29/417 ,  H01L23/528

Abstract: A semiconductor device may include first and second active patterns, each including a center portion and an edge portion, the center portion of the first active pattern and the edge portion of the second active pattern adjacent to each other, a device isolation pattern between the first and second active patterns, a bit line node contact on the center portion of the first active pattern, a bit line on the bit line node contact, a storage node contact on the edge portion of the second active pattern, a bit line spacer between the bit line and the storage node contact, and a gapfill insulating pattern between a lower portion of the bit line spacer and the storage node contact. The center portion of the first active pattern may include a center oxide region in an upper portion thereof.

公开(公告)号：US20250072064A1

公开(公告)日：2025-02-27

申请号：US18945603

申请日：2024-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyemi LEE ,  Seongjae GO ,  Hyeonjoo SONG ,  Sunjoong PARK ,  Hanyong PARK

IPC: H01L29/06 ,  G11C5/06 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device including a peripheral circuit layer on a substrate; a lower stack and upper stack on the substrate; a stopper layer on the upper stack and including an insulating material; an upper mold layer on the stopper layer; a cell channel structure extending through the layers, a side surface of the cell channel structure contacting the stopper layer; first and second capping layers; a word line separation structure including a protrusion protruding toward the stopper layer; and a bit line contact plug connected to the cell channel structure, wherein an inner side surface of the stopper layer is offset from an inner side surface of the upper stack, and in contact with the word line separation structure.

公开(公告)号：US20250071993A1

公开(公告)日：2025-02-27

申请号：US18605147

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunji Kim ,  Sehee Jang ,  Jeehoon Han

IPC: H10B43/27 ,  H10B41/27

Abstract: The present disclosure relates to three-dimensional (3D) semiconductor memory devices and electronic systems. An example 3D semiconductor memory device comprises a substrate that includes a cell array region and a connection region, a structure in which a plurality of dielectric layers and a plurality of gate electrodes are alternately stacked on the substrate, a plurality of dummy vertical structures that extend through the structure on the connection region, and a gate contact that extends through the structure on the connection region and is connected to one gate electrode of the plurality of gate electrodes. The gate contact is between the plurality of dummy vertical structures in a plan view. The gate contact includes a first portion and a plurality of second portions that extend between the plurality of dummy vertical structures.

公开(公告)号：US20250071992A1

公开(公告)日：2025-02-27

申请号：US18604586

申请日：2024-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Yong Lee ,  Se Hoon Lee ,  Jun Hyoung Kim ,  Ji Young Kim ,  Suk Kang Sung

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor memory device may include a cell substrate including a first surface and a second surface opposite to the first surface, and a landing pattern including a third surface and a fourth surface opposite to the third surface, with the landing pattern spaced apart from the cell substrate in a horizontal direction. The semiconductor memory device may include a plurality of gate electrodes sequentially stacked on the first surface and the third surface, a channel structure on the cell substrate, the channel structure extending vertically and intersecting the plurality of gate electrodes, an upper insulating film covering the second surface and the fourth surface, an input/output pad on the upper insulating film, the input/output pad overlapping at least a portion of the plurality of gate electrodes in the vertical direction, and a support contact extending through the upper insulating film and connecting the landing pattern and the input/output pad.