公开(公告)号：US20080129351A1

公开(公告)日：2008-06-05

申请号：US11803725

申请日：2007-05-15

Applicant: Nitin Chawla

Inventor： Nitin Chawla

IPC: H03L7/06 ,  H03K3/00

CPC classification number: H04B1/69 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/1976 ,  H03M7/3026 ,  H03M7/3042

Abstract: The present disclosure provides a spread spectrum clock generation system having a digitally controlled phase locked loop (PLL) and a digital frequency profile generator to create a near optimal frequency modulation profile for the purpose of achieving spectral flatness in the output frequency modulated clock. The circuit is combined with a multilevel error feedback noise shaping structure that provides the required noise transfer function for the quantization noise but maintains a unity gain all pass signal transfer function. This arrangement offers minimal degradation of the in-band signal-to-noise ratio (SNR) at the cost of higher out-of-band noise.

Abstract translation: 本公开提供了具有数字控制的锁相环（PLL）和数字频率分布生成器的扩频时钟生成系统，以便为了实现输出调制时钟的频谱平坦度而创建近似最佳的频率调制曲线。 该电路与多级误差反馈噪声整形结构相结合，为结构量化噪声提供所需的噪声传递函数，但保持单位增益全通信号传递功能。 这种布置以较高的带外噪声为代价降低了带内信噪比（SNR）的降低。

公开(公告)号：US20080111580A1

公开(公告)日：2008-05-15

申请号：US11897520

申请日：2007-08-30

Applicant: Ankit Kumar Rathi ,  Ankit Srivastava ,  Paras Garg

Inventor： Ankit Kumar Rathi ,  Ankit Srivastava ,  Paras Garg

IPC: H03K17/16

CPC classification number: H03K17/6872 ,  H03K17/04206 ,  H03K17/0822 ,  H03K17/165

Abstract: An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.

Abstract translation: 一种用于在驱动传输线负载的CMOS缓冲器的状态转变期间改善输出的输出缓冲器电路。 电路产生与负载传输线阻抗成比例的可变输出阻抗。 缓冲器包括输出级，例如用于接收输入信号并产生输出信号的上拉/下拉驱动器。 上拉/下拉驱动器由产生控制信号的电路偏置，并根据控制信号改变其电导率。 上拉/下拉驱动器最初提供相对较低的阻抗以在输出的初始过渡期间达到期望的电平，然后响应于控制信号缓慢地改变其阻抗以抑制振铃效应。 控制电路耦合到输入节点，输出节点和电源节点，以产生偏置上拉/下拉驱动器的控制信号。

公开(公告)号：US07372755B2

公开(公告)日：2008-05-13

申请号：US11102463

申请日：2005-04-08

Applicant: Swapnil Bahl ,  Balwant Singh

Inventor： Swapnil Bahl ,  Balwant Singh

IPC: G11C7/00

CPC classification number: G06F5/10 ,  G11C7/1006

Abstract: An improved on-chip storage memory and method for storing variable data bits, the memory including an on-chip storage memory system for storing variable data bits that has a memory for storing data bits, a wrapper for converting the memory into a first-in first-out (FIFO) memory, and a controller for performing operations on the memory. In operation, the memory is converted into a FIFO memory after storing data, and output logic selects data to be output in a serial manner.

Abstract translation: 一种用于存储可变数据位的改进的片上存储器和方法，所述存储器包括用于存储具有用于存储数据位的存储器的可变数据位的片上存储存储器系统，用于将存储器转换为先进先出 先进先出（FIFO）存储器和用于对存储器执行操作的控制器。 在操作中，存储器在存储数据之后被转换为FIFO存储器，并且输出逻辑选择要以串行方式输出的数据。

公开(公告)号：US07368976B2

公开(公告)日：2008-05-06

申请号：US11290619

申请日：2005-11-29

Applicant: Sushil K. Gupta ,  Paras Garg

Inventor： Sushil K. Gupta ,  Paras Garg

IPC: H03K3/01

CPC classification number: H03K3/011 ,  H03K3/3565 ,  H03K17/145 ,  H03K19/00384

Abstract: In the present invention an apparatus and method for providing compensation against temperature, process and supply voltage variation in MOS circuits has been proposed. The invention provides a change in process, temperature and voltage detection circuit, which controls the body bias and the drive of the devices in the CMOS circuit. The detection circuit is independent of any input or internal signal of the CMOS circuit to be controlled.

Abstract translation: 在本发明中，提出了一种用于对MOS电路中的温度，工艺和电源电压变化进行补偿的装置和方法。 本发明提供过程，温度和电压检测电路的变化，其控制CMOS电路中的器件的体偏置和驱动。 检测电路与要控制的CMOS电路的任何输入或内部信号无关。

公开(公告)号：US07353442B2

公开(公告)日：2008-04-01

申请号：US11102556

申请日：2005-04-08

Applicant: Swapnil Bahl ,  Balwant Singh

Inventor： Swapnil Bahl ,  Balwant Singh

IPC: G01R31/28

CPC classification number: G11C29/16 ,  G01R31/31724 ,  G11C29/006 ,  G11C29/12015 ,  G11C2029/1208 ,  G11C2029/5602

Abstract: An on-chip and at-speed tester for testing and characterization of different types of memories in an integrated circuit device, comprising a Centralized Flow Controller for automatically controlling the test operations for selected test programs, and Localized Signal Generators located inside each memory block and controlled by said Centralized Flow Controller for applying specified test patterns on the associated memory array.

Abstract translation: 一种用于在集成电路设备中测试和表征不同类型的存储器的片上和速度测试器，包括用于自动控制所选测试程序的测试操作的集中流量控制器和位于每个存储块内的定位信号发生器，以及 由所述集中流量控制器控制，用于在相关联的存储器阵列上应用指定的测试图案。

公开(公告)号：US07348802B2

公开(公告)日：2008-03-25

申请号：US11152822

申请日：2005-06-14

Applicant: Sunil C. Kasanyal ,  Rajat Chauhan

Inventor： Sunil C. Kasanyal ,  Rajat Chauhan

IPC: H03K19/0175

CPC classification number: H04L25/0292 ,  H03K19/00361 ,  H03K19/018528 ,  H04L25/0272

Abstract: A differential receiver includes a feedback circuit connected between an output node and one common node of the differential receiver to reduce the bandwidth and reject noise for a specific interval of time. In operation, a differential receiver bias current is controlled responsive to an output signal at the output node. Bias current is turned on during a steady-state mode with respect to the output signal, and is turned off, for a given delay period, in response to a transition mode with respect to the output signal.

Abstract translation: 差分接收器包括连接在输出节点和差分接收器的一个公共节点之间的反馈电路，以在特定的时间间隔内减少带宽和抑制噪声。 在操作中，响应于输出节点处的输出信号来控制差分接收器偏置电流。 在相对于输出信号的稳态模式期间，偏置电流被接通，并且响应于相对于输出信号的转换模式而在给定的延迟时段内被关断。

公开(公告)号：US20080068083A1

公开(公告)日：2008-03-20

申请号：US11900929

申请日：2007-09-12

Applicant: Pratap Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Ashish Sharma

Inventor： Pratap Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Ashish Sharma

IPC: H03F3/45

CPC classification number: H03F1/3211 ,  H03F3/45192 ,  H03F3/45659 ,  H03F2200/513 ,  H03F2203/45082 ,  H03F2203/45424 ,  H03F2203/45428 ,  H03F2203/45521 ,  H03F2203/45642 ,  H03F2203/45681

Abstract: Embodiments of the present invention provide a low voltage continuous time common mode feedback (CMFB) module, for low voltage operational amplifiers, providing good linearity, wide bandwidth and low systematic offset. The common mode feedback module includes a controlling module and an initializing module. The controlling module and the initializing module are parallel common mode feedback loops. The controlling module is a main CMFB loop and the initializing module is an auxiliary CMFB loop and both the loops work simultaneously. The controlling module and the initializing module receive a first differential input voltage and a second differential input voltage supplied by differential outputs of a main differential amplifier. Both the CMFB loops are low gain amplifiers in order to provide operation as linear as possible over the entire differential output operating range of the main differential amplifier.

Abstract translation: 本发明的实施例为低电压运算放大器提供低电压连续时间共模反馈（CMFB）模块，提供良好的线性度，宽带宽和低系统偏移。 共模反馈模块包括控制模块和初始化模块。 控制模块和初始化模块是并联共模反馈回路。 控制模块是主CMFB循环，初始化模块是辅助CMFB循环，两个循环同时工作。 控制模块和初始化模块接收由主差分放大器的差分输出提供的第一差分输入电压和第二差分输入电压。 CMFB环路都是低增益放大器，以便在主差分放大器的整个差分输出工作范围内提供尽可能线性的操作。

公开(公告)号：US07336213B2

公开(公告)日：2008-02-26

申请号：US11305328

申请日：2005-12-16

Applicant: Nikhil Gupta ,  Alok K. Mittal

Inventor： Nikhil Gupta ,  Alok K. Mittal

IPC: H03M1/50

CPC classification number: H03M1/52

Abstract: Polarity independent precision measurement of an input voltage signal is accomplished using a voltage integrating circuit that receives a first positive reference voltage and the input voltage signal, wherein the first positive reference voltage is greater in magnitude than the input voltage signal. A resetting circuit is coupled to the voltage integrating circuit for stabilizing its output. A pair of comparators, each connected to the output of the voltage integrating circuit, make voltage comparisons against a second reference voltage and a third reference voltage respectively, wherein the second and third reference voltages are greater in magnitude than the first reference voltage. A time interval measurement circuit receives the outputs of the pair of comparators, and operates to measure the time taken for the output of the voltage integrating circuit to transit to the second reference voltage level and the third reference voltage level. The time interval measurement circuit provides an output for controlling the resetting circuit.

Abstract translation: 使用接收第一正参考电压和输入电压信号的电压积分电路来实现输入电压信号的极性独立精密测量，其中第一正参考电压的幅度大于输入电压信号。 复位电路耦合到电压积分电路以稳定其输出。 一对比较器分别连接到电压积分电路的输出端，分别对第二参考电压和第三参考电压进行电压比较，其中第二和第三参考电压的幅度大于第一参考电压。 时间间隔测量电路接收一对比较器的输出，并且操作以测量电压积分电路的输出转移到第二参考电压电平和第三参考电压电平所花费的时间。 时间间隔测量电路提供用于控制复位电路的输出。

公开(公告)号：US07327163B2

公开(公告)日：2008-02-05

申请号：US11110654

申请日：2005-04-20

Applicant: Rajat Chauhan ,  Sunil C. Kasanyal

Inventor： Rajat Chauhan ,  Sunil C. Kasanyal

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: H03K19/018521 ,  H03K19/0013

Abstract: A voltage translator circuit for low level to high level voltage translation includes a plurality of transistors coupled to an inverter for receiving a common input signal at an input node of the plurality of transistors and passing a translated output signal to the output node of the plurality of transistors. A latch circuit is connected between a first node at the output node of the plurality of transistors and a second node that is connected to a feedback element at an input side of the plurality of transistors to form a feedback circuit that minimizes static power dissipation.

Abstract translation: 用于低电平到高电平电压转换的电压转换器电路包括耦合到反相器的多个晶体管，用于在多个晶体管的输入节点处接收公共输入信号，并将转换后的输出信号传送到多个晶体管的输出节点 晶体管。 锁存电路连接在多个晶体管的输出节点处的第一节点和连接到多个晶体管的输入侧的反馈元件的第二节点，以形成最小化静态功耗的反馈电路。

公开(公告)号：US07325100B2

公开(公告)日：2008-01-29

申请号：US11264301

申请日：2005-10-31

Applicant: Gaurav Dhiman ,  Gaurav Kapoor

Inventor： Gaurav Dhiman ,  Gaurav Kapoor

IPC: G06F12/00 ,  G06F1/32

CPC classification number: G06F1/30 ,  G06F1/3203 ,  G06F9/4418

Abstract: An apparatus for entering and exiting low power mode comprising a processor having a cache; a power management mechanism connected to said processor for controlling a plurality of power management states, at least one of said power management states being a low latency low power state; a memory subsystem including a self sustaining mechanism connected to said processor for retaining data during said low power state; a pre-fetching routine in said memory subsystem for loading instructions into a cache prior to entering said low power state; a disabling mechanism in said processor for disabling any interrupts that may disturb said pre-fetched instructions; an enabling routine in said memory subsystem for initiating the self sustaining operation of said memory subsystem; a detecting routine connected to said processor for sensing a trigger to exit from said low power state; and a restoring routine in said power management mechanism for restoring the clock of said apparatus; thereby said processor disabling said self sustaining operation and resuming normal operation at the end of said low power state.

Abstract translation: 一种用于进入和退出低功率模式的装置，包括具有高速缓存的处理器; 电源管理机构，连接到所述处理器，用于控制多个电源管理状态，所述电源管理状态中的至少一个是低延迟低功率状态; 存储器子系统，包括连接到所述处理器的自持机构，用于在所述低功率状态期间保持数据; 所述存储器子系统中的预取程序用于在进入所述低功率状态之前将指令加载到高速缓存器中; 所述处理器中的禁用机制用于禁止可能干扰所述预取指令的任何中断; 所述存储器子系统中的启动例程用于启动所述存储器子系统的自我维持操作; 连接到所述处理器的检测程序，用于感测从所述低功率状态退出的触发器; 以及所述电源管理机构中的恢复所述设备的时钟的恢复程序; 从而所述处理器禁止所述自维持操作并在所述低功率状态结束时恢复正常操作。