公开(公告)号：US10122384B2

公开(公告)日：2018-11-06

申请号：US15157814

申请日：2016-05-18

申请人： ARM Limited

发明人： Liangzhen Lai ,  Vikas Chandra ,  Gary Dale Carpenter

IPC分类号： G11C29/00 ,  H03M13/29 ,  H03M13/27

摘要： Various implementations described herein are directed to a memory device. The memory device includes a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device includes a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit interleaves data bits from multiple different data words and stores modified data words based on the multiple different data words.

公开(公告)号：US10083833B1

公开(公告)日：2018-09-25

申请号：US15629684

申请日：2017-06-21

申请人： ARM Limited

发明人： Ronald Paxton Preston ,  Marlin Wayne Frederick, Jr.

IPC分类号： H01L21/033

CPC分类号： H01L21/0338 ,  G03F1/36 ,  G03F7/70441 ,  G06F17/5036 ,  G06F17/5068

摘要： Various implementations described herein are directed to a method for manufacturing an integrated circuit. The method may include defining multiple lithographic regions for the integrated circuit, and the multiple lithographic regions may include a first lithographic region and a second lithographic region. The method may include defining an anchor in the first lithographic region and defining a target in the second lithographic region. The method may include defining a spacing interval between the anchor and the target. The method may include inserting an integration fill in the spacing interval.

公开(公告)号：US10083269B2

公开(公告)日：2018-09-25

申请号：US14528314

申请日：2014-10-30

申请人： ARM Limited

发明人： Paul De Dood ,  Marlin Wayne Frederick ,  Jerry Chaoyuan Wang ,  Brian Douglas Ngai Lee ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Yanbin Jiang ,  Emmanuel Jean Marie Olivier Pacaud ,  Matthieu Domonique Henri Pauly ,  Sylvia Xiuhui Li ,  Thanusree Achuthan ,  Daniel J. Albers ,  David William Granda

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.

公开(公告)号：US10077648B2

公开(公告)日：2018-09-18

申请号：US14446140

申请日：2014-07-29

申请人： GYRODATA, Incorporated

发明人： Adrián Guillermo Ledroz ,  John Lionel Weston

IPC分类号： E21B47/022 ,  E21B7/04 ,  E21B7/10 ,  G01C19/02

CPC分类号： E21B47/022 ,  E21B7/04 ,  E21B7/10 ,  G01C19/02

摘要： Systems and methods are provided for producing a continuous survey of a previously drilled portion of a wellbore. The method includes receiving a plurality of stationary survey measurements taken at a corresponding plurality of locations along the portion of the wellbore. The method further includes receiving at least one continuous survey including a plurality of continuous survey measurements taken between a pair of stationary survey measurements of the plurality of stationary survey measurements. The method further includes combining the plurality of stationary survey measurements and the plurality of continuous survey measurements to produce the continuous survey of the portion of the wellbore.

公开(公告)号：US09977145B2

公开(公告)日：2018-05-22

申请号：US14832903

申请日：2015-08-21

申请人： Gyrodata, Incorporated

发明人： Nigel John Dennis Kilshaw ,  Donald Ian Carruthers ,  Peter Allen ,  Walter Edward Somerville Davey

IPC分类号： G01V5/12 ,  G01V5/06

CPC分类号： G01V5/12 ,  G01V5/06

摘要： A wellbore survey tool and methods for estimating a direction of highest gamma ray intensity of a gamma ray distribution are provided. The tool includes a body having a center axis. The body is configured to be placed within a wellbore. The tool further includes a plurality of gamma ray detectors within the body. Each detector of the plurality of gamma ray detectors has a direction of maximum gamma ray sensitivity with the direction having a non-zero component perpendicular to the center axis. The non-zero components of the plurality of gamma ray detectors are spaced circumferentially about the center axis.

公开(公告)号：US09970151B2

公开(公告)日：2018-05-15

申请号：US15073446

申请日：2016-03-17

申请人： Serviam U, LLC

发明人： Roberto Trevino Camargo

IPC分类号： D06F95/00 ,  D06F35/00 ,  B65D85/18 ,  B65D33/01 ,  B65D33/25 ,  B65D30/06

CPC分类号： D06F95/006 ,  D06F35/005

摘要： A system and method for a laundry wash bag can comprise an lattice walls, a solid wall portion and a plurality of nodules. The lattice walls can form a plurality of polygonal perforations. The lattice walls can be capable of containing one or more garments. The solid wall portion can attach on a portion of the lattice walls. The solid wall portion can comprise a fastener that is capable of opening and closing the lattice walls to allow receiving of the one or more garments. The plurality of nodules can be placed within the inner surface of the lattice walls. The plurality of nodules can be capable of rubbing with the one or more garments. The plurality of nodules can be capable of reduce wrinkles during the drying cycle.

公开(公告)号：US09953701B1

公开(公告)日：2018-04-24

申请号：US15439899

申请日：2017-02-22

申请人： ARM Limited

发明人： Fakhruddin Ali Bohra ,  Lalit Gupta ,  Shri Sagar Dwivedi ,  Jitendra Dasani

IPC分类号： G11C11/34 ,  G11C11/419 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C11/418

摘要： An SRAM with a first bitcell array having a first density and a first access speed, and a second bitcell array having a second density larger than the first density and a second access speed less than the first access speed. The SRAM further includes a first set of wordline drivers coupled to the first bitcell array, a second set of wordline drivers coupled to the second bitcell array, and a row decoder coupled to both the first and second bitcell arrays.

公开(公告)号：US09929149B2

公开(公告)日：2018-03-27

申请号：US15188544

申请日：2016-06-21

申请人： ARM Limited

发明人： Saurabh Pijuskumar Sinha ,  Robert Campbell Aitken ,  Brian Tracy Cline ,  Gregory Munson Yeric ,  Kyungwook Chang

IPC分类号： H01L27/06 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48

CPC分类号： H01L27/0688 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/14 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13025 ,  H01L2224/73207

摘要： Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.

公开(公告)号：US09911510B1

公开(公告)日：2018-03-06

申请号：US15288832

申请日：2016-10-07

申请人： ARM Limited

发明人： Jungtae Kwon ,  Young Suk Kim ,  Vivek Nautiyal ,  Pranay Prabhat ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Satinderjit Singh ,  Lalit Gupta

IPC分类号： G11C29/00 ,  G11C11/418 ,  G11C11/412

CPC分类号： G11C29/76 ,  G11C8/04 ,  G11C11/413 ,  G11C11/418

摘要： Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.

公开(公告)号：US09893517B2

公开(公告)日：2018-02-13

申请号：US14570142

申请日：2014-12-15

申请人： ARM Limited

发明人： Ranabir Dey ,  Abhinav Kumar ,  Vijaya Kumar Vinukonda ,  Fabrice Blanc

IPC分类号： H02H9/00 ,  H02H9/04 ,  H01L29/78 ,  H01L27/02

CPC分类号： H02H9/046 ,  H01L27/0285 ,  H01L29/78

摘要： Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.