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    Methods of manufacturing semiconductor devices
    64.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US08815672B2

    公开(公告)日：2014-08-26

    申请号：US13223783

    申请日：2011-09-01

    Applicant: Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang

    Inventor： Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang

    IPC: H01L21/8238

    CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7843

    Abstract: A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.

    Abstract translation: 一种制造半导体器件的方法包括分别在第一和第二区域的衬底上形成第一和第二栅极结构，通过第一高密度等离子体工艺在衬底上形成第一覆盖层，使得第一覆盖层覆盖第一 以及除了其侧壁之外的第二栅极结构，去除第一区域中的第一覆盖层的一部分，使用第一栅极结构去除第一区域中的衬底的上部，以形成第一沟槽，并形成 第一外延层，以填充第一沟槽。

    Methods of fabricating MOS transistors having recesses with elevated source/drain regions
    66.
    发明授权
    Methods of fabricating MOS transistors having recesses with elevated source/drain regions 有权
    制造具有升高的源极/漏极区域的凹槽的MOS晶体管的方法

    公开(公告)号：US08039350B2

    公开(公告)日：2011-10-18

    申请号：US12582073

    申请日：2009-10-20

    Applicant: Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    Inventor： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC: H01L21/336

    CPC classification number: H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

    Abstract: Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

    Abstract translation: 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。

    Fin field effect transistors with low resistance contact structures
    67.
    发明授权
    Fin field effect transistors with low resistance contact structures 有权
    具有低电阻接触结构的Fin场效应晶体管

    公开(公告)号：US07385237B2

    公开(公告)日：2008-06-10

    申请号：US11076185

    申请日：2005-03-09

    Applicant: Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

    Inventor： Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

    IPC: H01L29/08

    CPC classification number: H01L29/7851 ,  H01L29/66795

    Abstract: Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure on the substrate that extends laterally in a second direction to cover a portion of the active pattern and a conductive layer that is on at least portions of side surfaces of the active pattern that are adjacent a side portion of the gate structure. The conductive layer may comprise a semiconductor layer, and the semiconductor layer may be in electrical contact with a contact pad. In other embodiments, the conductive layer may comprise a contact pad.

    Abstract translation: 提供鳍式FET半导体器件，其包括衬底，从衬底垂直突出并且在第一方向上横向延伸的有源图案，具有比活动图案的顶表面低的顶表面的器件隔离层， 基板上的栅极结构，其在第二方向上横向延伸以覆盖有源图案的一部分，以及位于与栅极结构的侧部相邻的有源图案的至少部分侧表面上的导电层。 导电层可以包括半导体层，并且半导体层可以与接触焊盘电接触。 在其它实施例中，导电层可以包括接触垫。

    Fin-field effect transistors (Fin-FETs) having protection layers
    68.
    发明申请
    Fin-field effect transistors (Fin-FETs) having protection layers 有权
    具有保护层的鳍场效应晶体管（Fin-FET）

    公开(公告)号：US20070034925A1

    公开(公告)日：2007-02-15

    申请号：US11586225

    申请日：2006-10-25

    Applicant: Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

    Inventor： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

    IPC: H01L29/94

    CPC classification number: H01L29/7851 ,  H01L29/66795

    Abstract: Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is provided on the first insulation layer and a second insulation layer is provided on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin.

    Abstract translation: 提供了场效应晶体管（Fin-FET）。 翅片设置在集成电路基板上。 翅片限定集成电路基板上的沟槽。 第一绝缘层设置在沟槽中，使得第一绝缘层的表面在鳍片的暴露翅片侧壁的表面下方凹进。 保护层设置在第一绝缘层上，第二绝缘层设置在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。

    Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
    70.
    发明授权
    Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage 失效
    使用保护层制造鳍状场效应晶体管以减少蚀刻损伤的方法

    公开(公告)号：US07074662B2

    公开(公告)日：2006-07-11

    申请号：US10869764

    申请日：2004-06-16

    Applicant: Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    Inventor： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    IPC: H01L21/8238

    CPC classification number: H01L29/7851 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a vertical fin protruding from the substrate. A buffer oxide liner is formed on a top surface and on sidewalls of the fin. A trench is then formed on the substrate, where at least a portion of the fin protrudes from a bottom surface of the trench. The trench may be formed by forming a dummy gate on at least a portion of the fin, forming an insulation layer on the fin surrounding the dummy gate, and then removing the dummy gate to expose the at least a portion of the fin, such that the trench is surrounded by the insulation layer. The buffer oxide liner is then removed from the protruding portion of the fin, and a gate is formed in the trench on the protruding portion of the fin.

    Abstract translation: 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底突出的垂直翅片。 缓冲氧化物衬垫形成在翅片的顶表面和侧壁上。 然后在衬底上形成沟槽，其中鳍的至少一部分从沟槽的底表面突出。 可以通过在鳍片的至少一部分上形成伪栅极来形成沟槽，在围绕虚拟栅极的鳍片上形成绝缘层，然后去除伪栅极以暴露鳍片的至少一部分，使得 沟槽被绝缘层包围。 然后从鳍片的突出部分去除缓冲氧化物衬垫，并且在鳍片的突出部分上的沟槽中形成栅极。

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