公开(公告)号：US06882009B2

公开(公告)日：2005-04-19

申请号：US10230055

申请日：2002-08-29

申请人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

发明人： Ming-Dou Ker ,  Tang-Kui Tseng ,  Hsin-Chin Jiang ,  Chyh-Yih Chang ,  Jeng-Jie Peng

IPC分类号： H01L21/265 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/07 ,  H01L29/10 ,  H01L21/01 ,  H01L23/62

CPC分类号： H01L27/0277 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0716 ,  H01L29/1079 ,  H01L29/1087 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

公开(公告)号：US06633087B2

公开(公告)日：2003-10-14

申请号：US09818455

申请日：2001-03-27

申请人： Ming-Dou Ker ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC分类号： H01L2940

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L24/48 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

摘要： A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

摘要翻译： 一种用于半导体器件的低电容焊盘。 在衬底中形成扩散区，并且在衬底上形成接合焊盘并与扩散区对准。 接合焊盘由堆叠的金属层和金属层制成。 堆叠的金属层由多个金属层和多个电介质层制成，并且金属层和电介质层交替堆叠。 堆叠在层叠金属层中的金属层形成有小面积。 堆叠在层叠金属层中的每个金属层通过插塞与相邻的金属层耦合

公开(公告)号：US06465283B1

公开(公告)日：2002-10-15

申请号：US09654810

申请日：2000-09-05

申请人： Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang ,  Jeng-Jie Peng

发明人： Chyh-Yih Chang ,  Ming-Dou Ker ,  Hsin-Chin Jiang ,  Jeng-Jie Peng

IPC分类号： H01L21332

CPC分类号： H01L21/823814 ,  H01L21/823878 ,  H01L27/0921

摘要： A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.

摘要翻译： 使用闭锁注入来提高CMOS电路中的闭锁抑制的结构和制造方法。 通过在寄生SCR的阴极和阳极上执行离子注入工艺来提高寄生SCR导通路径的阻抗，这可能引起闩锁现象。 因此，寄生SCR因此不容易以更高的抗噪声进行。 因此，可以提高闩锁抗扰度。 此外，可以进行离子注入工艺以实现防止闩锁效应的目的，而不消耗更多的布局面积，从而大大增强了电路设计的灵活性。

公开(公告)号：US06448641B2

公开(公告)日：2002-09-10

申请号：US09329648

申请日：1999-06-09

申请人： Ming-Dou Ker ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC分类号： H01L2312

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L24/48 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

摘要： A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

摘要翻译： 一种用于半导体器件的低电容焊盘。 在衬底中形成扩散区，并且在衬底上形成接合焊盘并与扩散区对准。 接合焊盘由堆叠的金属层和金属层制成。 堆叠的金属层由多个金属层和多个电介质层制成，并且金属层和电介质层交替堆叠。 堆叠在层叠金属层中的金属层形成有小面积。 堆叠在堆叠金属层中的每个金属层通过插塞与相邻的金属层耦合。

公开(公告)号：US06335698B1

公开(公告)日：2002-01-01

申请号：US09414943

申请日：1999-10-08

申请人： Ming-Dou Ker ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC分类号： H03M136

CPC分类号： H03M1/361

摘要： A flash analog-to-digital converter having a plurality of inverter circuits each comprising a programmable non-volatile memory cell and a load. The voltage values to be compared with the input voltage are threshold voltages individually programmable and stored on the plurality of memory cells. A comparison with the input voltage is performed by each of the memory cells, which are turned off to generate the value of logic “1” at an output when the input voltage is lower than the threshold voltage, and are turned on to generate the value of logic “0” at an output when the input voltage is greater than the threshold voltage.

摘要翻译： 一种具有多个逆变器电路的闪存模数转换器，每个逆变器电路各自包括可编程非易失性存储单元和负载。 要与输入电压进行比较的电压值是单独可编程并存储在多个存储单元上的阈值电压。 与输入电压的比较由每个存储单元执行，每个存储单元被关闭以在输入电压低于阈值电压时在输出端产生逻辑“1”的值，并被导通以产生该值 当输入电压大于阈值电压时，输出端的逻辑“0”。

公开(公告)号：US08431999B2

公开(公告)日：2013-04-30

申请号：US13072138

申请日：2011-03-25

申请人： Yu-Shu Shen ,  Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Yu-Shu Shen ,  Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L23/62 ,  H01L21/336

CPC分类号： H01L27/0255 ,  H01L29/861

摘要： A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.

摘要翻译： 公开了一种低电容瞬态电压抑制器。 抑制器包括N型重掺杂衬底和形成在衬底上的外延层。 形成在外延层中的至少一个转向二极管结构包括二极管轻掺杂阱和第一P型轻掺杂阱，其中在二极管轻掺杂阱中形成P型重掺杂区，并且第一N型重掺杂阱 在第一P型轻掺杂阱中形成掺杂区域和第二P型重掺杂区域。 在外延层中形成具有两个N型重掺杂区的第二P型轻掺杂阱。 此外，在外延层中形成N型重掺杂阱和至少一个深隔离沟槽，其中沟槽的深度大于或等于所有掺杂阱的深度，以便分离至少一个掺杂的 好。

公开(公告)号：US20130003242A1

公开(公告)日：2013-01-03

申请号：US13612253

申请日：2012-09-12

申请人： Kun-Hsien LIN ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Kun-Hsien LIN ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H3/22

CPC分类号： H02H9/046 ,  H05K1/0259

摘要： A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage.One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts.

摘要翻译： 公开了一种用于多个引脚分配的瞬态电压抑制器（TVS）。 抑制器包括彼此并联的至少两个级联二极管电路和与每个级联二极管电路并联并与低电压连接的静电放电钳位元件。 一个级联二极管电路与高电压连接，其他级联二极管电路分别与I / O引脚相连。 每个级联二极管电路还包括级联到第一二极管的第一二极管和第二二极管，其中第一二极管和第二二极管之间的节点与高电压或一个I / O引脚连接。 本发明的设计可以满足多个限制要求。 它是TVS零件的灵活不同的引脚分配。

公开(公告)号：US08237193B2

公开(公告)日：2012-08-07

申请号：US12837128

申请日：2010-07-15

申请人： Che-Hao Chuang ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

发明人： Che-Hao Chuang ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L29/06

CPC分类号： H01L27/0255

摘要： A lateral transient voltage suppressor for low-voltage applications. The suppressor includes an N-type heavily doped substrate and at least two clamp diode structures horizontally arranged in the N-type heavily doped substrate. Each clamp diode structure further includes a clamp well arranged in the N-type heavily doped substrate and having a first heavily doped area and a second heavily doped area. The first and second heavily doped areas respectively belong to opposite conductivity types. There is a plurality of deep isolation trenches arranged in the N-type heavily doped substrate and having a depth greater than depth of the clamp well. The deep isolation trenches can separate each clamp well. The present invention avoids the huge leakage current to be suitable for low-voltage application.

摘要翻译： 用于低电压应用的横向瞬态电压抑制器。 抑制器包括N型重掺杂衬底和水平地布置在N型重掺杂衬底中的至少两个钳位二极管结构。 每个钳位二极管结构还包括在N型重掺杂衬底中布置的具有第一重掺杂区域和第二重掺杂区域的钳位阱。 第一和第二重掺杂区域分别属于相反的导电类型。 在N型重掺杂衬底中布置有多个深的隔离沟槽，其深度大于夹具阱的深度。 深的隔离沟槽可以很好地分离每个夹具。 本发明避免了巨大的漏电流适合于低电压应用。

公开(公告)号：US08217462B2

公开(公告)日：2012-07-10

申请号：US12888151

申请日：2010-09-22

申请人： Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L23/62

CPC分类号： H01L29/8613 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/866

摘要： The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area.

公开(公告)号：USRE43215E1

公开(公告)日：2012-02-28

申请号：US11598154

申请日：2006-11-09

申请人： Ming-Dou Ker ,  Jeng-Jie Peng ,  Hsin-Chin Jiang

发明人： Ming-Dou Ker ,  Jeng-Jie Peng ,  Hsin-Chin Jiang

IPC分类号： H01L23/62

CPC分类号： H01L27/0277 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and/or varying channel lengths in the layout structure.

摘要翻译： 本发明涉及一种具有改进的ESD稳健性的静电放电（ESD）器件，用于保护I / O单元库中的输出缓冲器。 根据本发明的ESD装置使用新颖的I / O单元布局结构来实现导通抑制方法，其通过添加拾取扩散区域和/或改变来降低ESD保护MOS晶体管的导通速度 通道长度在布局结构中。