公开(公告)号：US20240127882A1

公开(公告)日：2024-04-18

申请号：US18497149

申请日：2023-10-30

Applicant: Rambus Inc.

Inventor： Thomas VOGELSANG ,  John Eric Linstadt ,  Liji Gopalakrishnan

IPC: G11C11/408 ,  G06F13/42 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4085 ,  G06F13/4282 ,  G11C11/4091 ,  G11C11/4094

Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

公开(公告)号：US20240119989A1

公开(公告)日：2024-04-11

申请号：US18375810

申请日：2023-10-02

Applicant: Rambus Inc.

Inventor： Steven C. WOO ,  Michael Raymond MILLER

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/408

Abstract: Row hammer is mitigated by issuing, to a memory device, mitigation operation (MOP) commands in order to cause the refresh of rows at a specified vicinity of a suspected aggressor row. These mitigation operation commands are each associated with respective row addresses that indicate the suspected aggressor row and an indicator of which neighbor row in the vicinity of the suspected aggressor row is to be refreshed. The mitigation operation commands are issued in response to a fixed number of activate commands. The suspected aggressor row is selected by randomly choosing, with equal probability, one of the N previous activate commands to supply its associated row address as the suspected aggressor row address. The neighbor row may be selected randomly with a probability that diminishes inversely with the distance between the suspected aggressor row and the neighbor row.

公开(公告)号：US20240111457A1

公开(公告)日：2024-04-04

申请号：US18496887

申请日：2023-10-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: G06F3/06 ,  G06F13/16 ,  G11C5/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/00

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

公开(公告)号：US20240111449A1

公开(公告)日：2024-04-04

申请号：US18367789

申请日：2023-09-13

Applicant: RAMBUS INC.

Inventor： Christopher Haywood ,  Frederick A. Ware

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0673

Abstract: A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel. The first memory module buffers and repeats signals received on the primary and secondary interfaces to enable communications between the memory controller and the secondary memory module.

公开(公告)号：US11949539B2

公开(公告)日：2024-04-02

申请号：US17516502

申请日：2021-11-01

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Abhijit Abhyankar

IPC: H04L25/03 ,  G06F3/05 ,  G06F3/06 ,  G11C19/00

CPC classification number: H04L25/03057 ,  G06F3/05 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G11C19/00 ,  H04L25/03146 ,  H04L25/03878

Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

公开(公告)号：US11947474B2

公开(公告)日：2024-04-02

申请号：US17830838

申请日：2022-06-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1673 ,  G06F13/1678 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US11942182B2

公开(公告)日：2024-03-26

申请号：US18089668

申请日：2022-12-28

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC: G11C7/10 ,  G11C5/04

CPC classification number: G11C7/1093 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1066

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

公开(公告)号：US11940857B2

公开(公告)日：2024-03-26

申请号：US18068437

申请日：2022-12-19

Applicant: Rambus Inc.

Inventor： Deborah Lindsey Dressler ,  Julia Kelly Cline ,  Wayne Frederick Ellis

IPC: G06F1/28 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F13/42 ,  G11C5/06

CPC classification number: G06F1/28 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/4273 ,  G11C5/063

Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

公开(公告)号：US11928020B2

公开(公告)日：2024-03-12

申请号：US18095341

申请日：2023-01-10

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/16 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

公开(公告)号：US20240080016A1

公开(公告)日：2024-03-07

申请号：US18236857

申请日：2023-08-22

Applicant: Rambus Inc.

Inventor： Cosmin IORGA ,  Ruibing ZHANG

IPC: H03H11/04

CPC classification number: H03H11/04

Abstract: A pulse filter circuit is configured to eliminate pulses that are less than a specified duration and pass those that are greater than the specified duration. A buffer receives a signal and applies the buffered signal to a resistance-capacitance charging-discharging circuit (e.g., RC filter). When the output of the RC filter has, in response to the buffered signal, charged or discharged, as appropriate, to cause the output of a slicer to change, logic circuitry controls switching circuitry to pull the output of the RC filter to be fully charged or discharged, respectively. In this manner, pulses that are too short to charge/discharge the RC filter enough to cross the threshold of the slicer do not reach the slicer circuit output, but pulses that are long enough to cross the slicer threshold are transmitted by the slicer.