Method and system for frequency up-conversion with modulation embodiments
    65.
    发明申请
    Method and system for frequency up-conversion with modulation embodiments 有权
    具有调制实施例的用于上变频的方法和系统

    公开(公告)号:US20050136861A1

    公开(公告)日:2005-06-23

    申请号:US11049057

    申请日:2005-02-03

    CPC classification number: H03D7/00 H03C1/62 H04B1/04 H04B7/12 H04B2001/0491

    Abstract: A method and system is described wherein an information signals is gated at a frequency that is a sub-harmonic of the frequency of the desired output signal. In the modulation embodiments, the information signal is modulated as part of the up-conversion process. In a first modulation embodiment, one information signal is phase modulated onto the carrier signal as part of the up-conversion process. In a second modulation embodiment, two information signals are multiplied, and, as part of the up-conversion process, one signal is phase modulated onto the carrier and the other signal is amplitude modulated onto the carrier. In a third modulation embodiment, one information signal is phase modulated onto the “I” phase of the carrier signal as part of the up-conversion process and a second information signal is phase modulated onto the “Q” phase of the carrier as part of the up-conversion process. In a fourth modulation embodiment, four information signals are phase and amplitude modulated onto the “I” and “Q” phases of the carrier as part of the up-conversion process. There are at least two implementations of each of the aforementioned embodiments.

    Abstract translation: 描述了一种方法和系统,其中信息信号以作为期望输出信号的频率的次谐波的频率门控。 在调制实施例中,作为上转换处理的一部分调制信息信号。 在第一调制实施例中,作为上转换处理的一部分,一个信息信号被相位调制到载波信号上。 在第二调制实施例中,将两个信息信号相乘,并且作为上转换处理的一部分,一个信号被相位调制到载波上,另一个信号被幅度调制到载波上。 在第三调制实施例中,一个信息信号作为上变频处理的一部分被相位调制到载波信号的“I”相上,并且第二信息信号被相位调制到载波的“Q”相,作为 上转换过程。 在第四调制实施例中,作为上转换处理的一部分,四个信息信号被相位和幅度调制到载波的“I”和“Q”相。 上述各实施例中至少有两个实现方式。

    Interim oxidation of silsesquioxane dielectric for dual damascene process
    66.
    发明授权
    Interim oxidation of silsesquioxane dielectric for dual damascene process 有权
    双重镶嵌工艺的倍半硅氧烷电介质的中间氧化

    公开(公告)号:US06479884B2

    公开(公告)日:2002-11-12

    申请号:US09893786

    申请日:2001-06-29

    CPC classification number: H01L21/76808 H01L2221/1063

    Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

    Abstract translation: 抗蚀剂显影剂可以攻击一些先进的介电材料,例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。 通过进行抗蚀剂剥离或蚀刻工艺,其中将反应物材料从电介质材料外部供应或释放出来,可以形成非常薄的中间材料的表面保护覆盖层,其不能抵抗显影剂或多种其它材料 这可能会损坏可流动的氧化物材料。 因此,与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容,以最小化导体电容并支持快速的信号传播和抗噪声性,即使导体彼此间隔紧密。

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