公开(公告)号：US20020116596A1

公开(公告)日：2002-08-22

申请号：US09915761

申请日：2001-07-26

Applicant: STMicroelectronics S.A.

Inventor： Jose Sanches ,  Marco Cornero ,  Miguel Santana ,  Philippe Guillaume ,  Jean-Marc Daveau ,  Thierry Lepley ,  Pierre Paulin ,  Michel Harrand

IPC: G06F009/30 ,  G06F012/00

CPC classification number: G06F9/3814 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract translation: 数字信号处理器被设计为执行可包括多达N个基本指令代码的可变大小的指令。 处理器包括存储器程序，其包括I个可寻址的并行连接的存储器组，其中以隔行方式记录程序的代码，以及用于读取布置成读取每个I存储体中的代码的程序存储器的电路 在读取指令的周期中。 用于读取程序存储器中的指令的循环包括读取包括要读取的指令代码或代码的代码序列，并且还可以包括属于后续指令的代码，该代码在指令被应用于执行单元之前被过滤。 数字信号处理器的程序存储器不包括任何无操作类型的代码。

公开(公告)号：US20020113643A1

公开(公告)日：2002-08-22

申请号：US09938289

申请日：2001-08-23

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: H03B001/00

CPC classification number: H03K5/1252

Abstract: A filtering circuit includes circuits for delivering first and second ramp-shaped signals when a logic signal to be filtered changes values, and includes logic circuits each with a switching threshold, for receiving the ramp-shaped signals. A memory unit delivers an output signal having a first value when outputs of the logic circuits have a first pair of values, and delivers a second value when the outputs of the logic circuits have a second pair of values. The filtering circuit may be applied to the filtering of an external clock signal in serial type memory devices.

Abstract translation: 滤波电路包括当待滤波的逻辑信号改变值时递送第一和第二斜坡形信号的电路，并且包括各自具有切换阈值的逻辑电路，用于接收斜坡形状的信号。 当逻辑电路的输出具有第一对值时，存储器单元递送具有第一值的输出信号，并且当逻辑电路的输出具有第二对值时传送第二值。 滤波电路可以应用于串行型存储器件中的外部时钟信号的滤波。

公开(公告)号：US20020113535A1

公开(公告)日：2002-08-22

申请号：US09997195

申请日：2001-11-28

Applicant: STMicroelectronics S.A.

Inventor： Franck Roche ,  Thierry Bouquier

IPC: H01J027/00

CPC classification number: G06F11/2236

Abstract: A microprocessor may be switchable between a normal mode and a test mode for performing a test program and may include a central processing unit (CPU) for saving contextual data in a stack of the microprocessor at the time of switching to the test mode. The CPU may deliver, at the beginning of the test program and on an input/output port, contextual data present in the stack beginning with the top of the stack. The CPU may also decrement a stack pointer by a value corresponding to a number of contextual data delivered.

Abstract translation: 微处理器可以在正常模式和用于执行测试程序的测试模式之间切换，并且可以包括用于在切换到测试模式时将上下文数据保存在微处理器的堆栈中的中央处理单元（CPU）。 CPU可以在测试程序开始时和在输入/输出端口上递送以堆栈顶部开头的堆栈中存在的上下文数据。 CPU也可以将堆栈指针减少与传递的上下文数据的数量相对应的值。

公开(公告)号：US20020109554A1

公开(公告)日：2002-08-15

申请号：US10021282

申请日：2001-10-30

Applicant: STMicroelectronics S.A.

Inventor： Bruno Gailhard ,  Olivier Ferrand

IPC: H03B001/00

CPC classification number: H03L7/0997 ,  G06F1/08

Abstract: A generator includes an oscillator for producing a clock signal from an N-bit control number. The oscillator includes a first group of cells, with each cell including at least one series connected inverter. A first selection circuit selects a variable number of the cells as a function of the most significant bits of the control number. The oscillator also includes a second group of cells, with each cell including at least one series connected inverter. A second selection circuit selects one of the cells as a function of the least significant bits of the control number. The selected cells of the first and second groups of cells are series connected to form a chain of inverters.

Abstract translation: 发生器包括用于从N位控制编号产生时钟信号的振荡器。 振荡器包括第一组单元，每个单元包括至少一个串联的反相器。 第一选择电路根据控制数的最高有效位选择可变数目的单元。 振荡器还包括第二组单元，每个单元包括至少一个串联连接的反相器。 第二选择电路根据控制号的最低有效位选择一个单元。 第一和第二组电池的所选择的电池被串联连接以形成一个反相器链。

公开(公告)号：US20020097093A1

公开(公告)日：2002-07-25

申请号：US10020010

申请日：2001-12-13

Applicant: STMicroelectronics S.A.

Inventor： Jerome Bourgoin ,  Frederic Goutti

IPC: H03F003/45

CPC classification number: H03G1/0035

Abstract: An amplifier includes an input stage with one or more input terminals for receiving a signal to be amplified, and an output terminal. An inverting gain stage includes an input terminal connected to the output terminal of the input stage, an output terminal for delivering an amplified signal, and a variable feedback resistor connected between the output terminal and input terminal thereof. The input stage is a transconductor stage biased by a current source. A transconductance thereof is set by a resistor of the current source so that the amplifier has a gain proportional to the product of the variable feedback resistor multiplied by the transconductance.

Abstract translation: 放大器包括具有用于接收要放大的信号的一个或多个输入端的输入级和输出端。 反相增益级包括连接到输入级的输出端的输入端，输出放大信号的输出端和连接在输出端和输入端之间的可变反馈电阻。 输入级是由电流源偏置的跨导级。 其跨导由电流源的电阻器设置，使得放大器具有与可变反馈电阻乘以跨导的乘积成比例的增益。

公开(公告)号：US20020093589A1

公开(公告)日：2002-07-18

申请号：US10032333

申请日：2001-12-18

Applicant: STMicroelectronics S.A.

Inventor： Arnaud Albella ,  Vincent Tauzia

IPC: H04N007/00 ,  H04N011/00

CPC classification number: H04N7/0882 ,  H04H60/27

Abstract: A method for storing pages of a teletext service, with at least one page being received by a storage circuit of a television receiver, is provided. The storage circuit includes a data memory for storing the at least one received page. The method includes extracting a reference number from the at least one received page, checking whether the at least one received page is a requested page, and evaluating contents of the data memory to decide whether the at least one received page is to be stored as a function of free space in the data memory and an importance of the at least one received page. The method also includes storing the at least one received page if it is decided that the at least one received page is to be stored.

Abstract translation: 一种用于存储图文电视服务的页面的方法，其中至少一个页面被电视接收机的存储电路接收。 存储电路包括用于存储至少一个接收页面的数据存储器。 该方法包括从至少一个接收到的页面提取参考号码，检查至少一个接收的页面是否是所请求的页面，以及评估数据存储器的内容，以决定是否将至少一个接收到的页面存储为 数据存储器中的可用空间的功能以及至少一个接收页面的重要性。 如果确定要存储至少一个接收到的页面，则该方法还包括存储至少一个接收到的页面。

公开(公告)号：US20020082791A1

公开(公告)日：2002-06-27

申请号：US10025372

申请日：2001-12-19

Applicant: STMicroelectronics S.A.

Inventor： Francois Tailliet

IPC: G06F019/00 ,  G01R035/00

CPC classification number: G11C29/028 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22 ,  G11C16/04 ,  G11C16/32 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A method for adjusting a duration of an internal timing signal in an integrated circuit with a value close to a typical value of the duration may include activating the internal timing signal in the integrated circuit and sequentially sending calibration values to an input of the integrated circuit. The expiration of the internal timing signal may determine the last calibration value received or being received, and the calibration data may be applied to a device for adjusting the duration of the internal timing signal.

Abstract translation: 用于以接近于持续时间的典型值的值调整集成电路中的内部定时信号的持续时间的方法可以包括激活集成电路中的内部定时信号并且顺序地将校准值发送到集成电路的输入。 内部定时信号的到期可以确定接收或正在接收的最后一个校准值，并且校准数据可以应用于用于调整内部定时信号的持续时间的设备。

公开(公告)号：US20020081374A1

公开(公告)日：2002-06-27

申请号：US09902497

申请日：2002-01-15

Applicant: STMicroelectronics S.A.

Inventor： Didier Dutartre ,  Patrick Jerier

IPC: B05D005/12

CPC classification number: C30B29/06 ,  C23C16/24 ,  C30B25/20

Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.

Abstract translation: 本发明涉及一种在硅基板上气相外延沉积硅的方法，该方法包括含有高浓度掺杂剂的区域，其中砷是砷，同时避免了砷的外延层的自掺杂，包括以下步骤：执行第一薄外延 沉积，然后退火; 第一外延沉积和退火的条件和持续时间使得砷扩散长度远低于在第一沉积中形成的层的厚度; 以及对所选择的持续时间进行第二外延沉积以获得期望的总厚度。

公开(公告)号：US20020076899A1

公开(公告)日：2002-06-20

申请号：US09920315

申请日：2001-08-01

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Michel Haond ,  Didier Dutartre

IPC: H01L021/76

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

Abstract translation: 提供了用于制造具有绝缘体上硅（SOI）或无硅（SON）结构的衬底的工艺，其可应用于半导体器件的制造，特别是诸如MOS，CMOS，BICMOS的晶体管 和HCMOS类型。 在制造工艺中，通过非选择性全晶片外延在衬底上生长多层叠层。 多层堆叠包括Ge或SiGe层上的硅层。 有源区被限定和掩蔽，并且绝缘垫被形成为以预定的间隔围绕每个有源区的周边定位并且抵靠有源区的侧壁放置。 绝缘沟槽被蚀刻，SiGe或Ge层被横向蚀刻，以便在硅层下方形成一个空洞。 沟槽填充有电介质。 在SOI结构的情况下，隧道填充有电介质。

公开(公告)号：US20020031848A1

公开(公告)日：2002-03-14

申请号：US09898523

申请日：2001-07-03

Applicant: STMicroelectronics S.A.

Inventor： Emmanuel Perrin ,  Herve Jaouen

IPC: H01L021/66 ,  H01L021/302 ,  H01L021/461 ,  G01R031/26

CPC classification number: B24B37/013 ,  B24B37/042 ,  B24B49/03 ,  B24B49/16 ,  H01L21/31053

Abstract: A method of determining the time for polishing the surface of an integrated circuit wafer on a polishing machine. A sample wafer is fabricated to include at least one high plateau and at least one low plateau joined by a sudden transition. At least one initial profile is topographically scanned, and the surface of the sample wafer is polished at a particular polishing pressure for a particular polishing time. The final profile of the polished layer is topographically scanned in the corresponding area, and the initial and final topographical scans of the sample wafer are converted into Fourier series. The surface of the wafer to be polished is topographically scanned, and the topographic scan of the wafer to be polished is converted into a Fourier series. The time for polishing the wafer to be polished is calculated from the Fourier series and the average thickness to be removed.

Abstract translation: 确定在抛光机上抛光集成电路晶片的表面的时间的方法。 制造样品晶片以包括至少一个高平台和至少一个通过突然过渡连接的低平台。 至少一个初始轮廓被地形扫描，并且在特定抛光压力下抛光样品晶片的表面以达到特定的抛光时间。 将抛光层的最终轮廓在相应的区域进行地形扫描，并将样品晶片的初始和最终的地形扫描转换为傅立叶级数。 将待研磨的晶片的表面进行地形扫描，并将要抛光的晶片的地形扫描转换为傅立叶级数。 抛光抛光晶片的时间由傅立叶级数和要去除的平均厚度计算。