公开(公告)号：US12001265B2

公开(公告)日：2024-06-04

申请号：US17483694

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Christopher T. Weaver ,  Indrani Paul ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Stephen V. Kosonocky ,  Thomas J. Gibney ,  Jose G. Cruz ,  Pravesh Gupta ,  Chintan S. Patel

IPC: G06F1/00 ,  G06F1/3234 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F1/3275 ,  G06F1/3265 ,  G06F3/0625 ,  G06F3/0635 ,  G06F3/0673 ,  G06F11/1469 ,  G06F2201/84

Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

公开(公告)号：US20240121192A1

公开(公告)日：2024-04-11

申请号：US18194311

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashwini Chandrashekhara Holla ,  Indrani Paul ,  Alexander J. Branover ,  Carlos Javier Moreira

IPC: H04L47/125 ,  H04L47/11

CPC classification number: H04L47/125 ,  H04L47/11

Abstract: The disclosed device for packet coalescing includes detecting a trigger condition for initiating packet coalescing of packet traffic and sending, to an endpoint device, a notification to start packet coalescing. The device can observe a status in response to starting the packet coalescing and report a performance of the packet coalescing. A system can include a controller that detects a trigger condition for packet coalescing and notifies an endpoint device via a notification register. The controller can read a status register to report, based on the read status, a packet coalescing performance. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240113914A1

公开(公告)日：2024-04-04

申请号：US17937262

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriram Sambamurthy ,  Indrani Paul ,  David Boardman Kramer ,  Madhusudan Chilakam

IPC: H04L12/46 ,  H04L49/109

CPC classification number: H04L12/4616 ,  H04L49/109

Abstract: An apparatus and method for efficiently performing power management for multiple clients of a semiconductor chip that supports remote manageability. In various implementations, a network interface receives a packet, and sends at least an indication of the packet to a manageability processing circuitry (MPC) of a processing node with multiple clients for processing tasks. The MPC determines whether a client or itself is a destination needed to process the packet. If the destination is the MPC, then packet processing is done by the MPC without involvement from the clients, which can be in an idle state. For example, the MPC can process a remote manageability packet requesting diagnostic information from one or more clients of the processing node. The network interface and the MPC use a sideband communication channel for data transmission, which foregoes lane training for further reduction in latency and power consumption.

公开(公告)号：US11886224B2

公开(公告)日：2024-01-30

申请号：US16945519

申请日：2020-07-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Leonardo De Paula Rosa Piga ,  Karthik Rao ,  Indrani Paul ,  Mahesh Subramony ,  Kenneth Mitchell ,  Dana Glenn Lewis ,  Sriram Sambamurthy ,  Wonje Choi

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/30

CPC classification number: G06F9/5027 ,  G06F9/48 ,  G06F9/4806 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5033 ,  G06F9/5044 ,  G06F9/5055 ,  G06F9/5094 ,  G06F9/30098 ,  G06F2209/5021

Abstract: A processing unit of a processing system compiles a priority queue listing of a plurality of processor cores to run a workload based on a cost of running the workload on each of the processor cores. The cost is based on at least one of a system usage policy, characteristics of the workload, and one or more physical constraints of each processor core. The processing unit selects a processor core based on the cost to run the workload and communicates an identifier of the selected processor core to an operating system of the processing system.

公开(公告)号：US11829222B2

公开(公告)日：2023-11-28

申请号：US17127681

申请日：2020-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriram Sambamurthy ,  Sriram Sundaram ,  Indrani Paul ,  Larry David Hewitt ,  Anil Harwani ,  Aaron Joseph Grenat ,  Dana Glenn Lewis ,  Leonardo Piga ,  Wonje Choi ,  Karthik Rao

IPC: G06F1/28 ,  G01R31/40 ,  G06F1/30

CPC classification number: G06F1/28 ,  G01R31/40 ,  G06F1/30

Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

公开(公告)号：US20230315188A1

公开(公告)日：2023-10-05

申请号：US17710521

申请日：2022-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor ,  Indrani Paul ,  Benjamin Tsien ,  Stephen V. Kosonocky ,  John P. Petry ,  Christopher T. Weaver

IPC: G06F1/3234

CPC classification number: G06F1/3234

Abstract: Methods and systems are disclosed for transitioning, by a hardware-based controller, a system on a chip (SoC) into different power states. Techniques disclosed include tracking, by the controller, metrics associated with the SoC and transitioning, by the controller, the SoC from a first power state to a second power state based on the tracked metrics. Were the total amount of power that is used by at least a portion of the transition between the first power state to the second power state and a time spent in the second power state is less than the total amount of power that would have been used by remaining in the first power state.

公开(公告)号：US20230205248A1

公开(公告)日：2023-06-29

申请号：US17560823

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Meeta Surendramohan Srivastav ,  Ashwini Chandrashekhara Holla ,  Alex Sabino Duenas ,  Xinzhe Li ,  Michael John Austin ,  Indrani Paul ,  Sriram Sambamurthy

IPC: G05F1/66 ,  G06F1/28

CPC classification number: G05F1/66 ,  G06F1/28

Abstract: An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.

公开(公告)号：US20230095622A1

公开(公告)日：2023-03-30

申请号：US17485194

申请日：2021-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Indrani Paul ,  Benjamin Tsien ,  Christopher T. Weaver ,  John P. Petry ,  Mihir Shaileshbhai Doctor ,  Thomas J. Gibney

IPC: G06F1/26 ,  G06F13/40

Abstract: A method and apparatus for isolating and restoring general-purpose input/output (GPIO) pads in a computer system includes identifying GPIO pads associated with the region responsive to an entry into a power-down state of a region of a circuit. The GPIO pads are isolated from one or more external circuits. Upon exit from the power-down state, each associated GPIO pad is restored to a current value.

公开(公告)号：US20230031295A1

公开(公告)日：2023-02-02

申请号：US17390475

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Thomas J. Gibney ,  Alexander J. Branover ,  Mihir Shaileshbhai Doctor ,  Xiaojie He ,  Indrani Paul ,  Benjamin Tsien ,  John P. Petry ,  Pitchaiah Katari

IPC: G06F1/324 ,  G06F1/3237 ,  G06F1/3218 ,  G06F1/08

Abstract: A disclosed technique includes triggering entry into a clock bypass mode, in which a bypass clock generator provides clock signals to functional elements and a primary clock generator does not provide clock signals to functional elements; and triggering exit from the clock bypass mode, in which the bypass clock generator does not provide clock signals to the functional elements and the primary clock generator does provide clock signals to the functional elements.

公开(公告)号：US11543877B2

公开(公告)日：2023-01-03

申请号：US17219097

申请日：2021-03-31

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Donny Yi ,  Oleksandr Khodorkovsky ,  Leonardo De Paula Rosa Piga ,  Wonje Choi ,  Dana G. Lewis ,  Sriram Sambamurthy

IPC: G06F1/32 ,  G06F1/3287

Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.