公开(公告)号：US06936882B1

公开(公告)日：2005-08-30

申请号：US10614001

申请日：2003-07-08

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L21/28097 ,  H01L21/823443 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795

Abstract: A semiconductor device includes a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer. The first device may include a first fin formed on the insulating layer, a first dielectric layer formed on the first fin, and a partially silicided gate formed over a portion of the first fin and the first dielectric layer. A second device also may be formed on the insulating layer. The second device may include a second fin formed on the insulating layer, a second dielectric layer formed on the second fin, and a fully silicided gate formed over a portion of the second fin and the second dielectric layer.

Abstract translation: 半导体器件包括衬底和形成在衬底上的绝缘层。 可以在绝缘层上形成第一器件。 第一器件可以包括形成在绝缘层上的第一鳍片，形成在第一鳍片上的第一电介质层和形成在第一鳍片和第一介电层的一部分上的部分硅化栅极。 也可以在绝缘层上形成第二器件。 第二器件可以包括形成在绝缘层上的第二鳍片，形成在第二鳍片上的第二介电层，以及形成在第二鳍片和第二介电层的一部分上的完全硅化栅极。

公开(公告)号：US06914277B1

公开(公告)日：2005-07-05

申请号：US10674400

申请日：2003-10-01

Applicant: Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by an insulating layer.

Abstract translation: 半导体器件包括N沟道器件和P沟道器件。 N沟道器件包括第一源极区，第一漏极区，第一鳍结构和栅极。 P沟道器件包括第二源极区，第二漏极区，第二鳍结构和栅极。 第二源极区域，第二漏极区域和第二鳍状结构通过绝缘层与第一源极区域，第一漏极区域和第一鳍片结构分离。

公开(公告)号：US20050056845A1

公开(公告)日：2005-03-17

申请号：US10975473

申请日：2004-10-29

Applicant: Krishnashree Achuthan ,  Shibly Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/321 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L21/3212 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681

Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

Abstract translation: FinFET型半导体器件包括翅片结构，其上形成相对薄的非晶硅层，然后形成未掺杂的多晶硅层。 半导体器件可以使用化学机械抛光（CMP）进行平面化，其中非晶硅层用作阻挡层以防止损坏鳍结构。

公开(公告)号：US20050029603A1

公开(公告)日：2005-02-10

申请号：US10633504

申请日：2003-08-05

Applicant: Bin Yu ,  Shibly Ahmed ,  Haihong Wang

Inventor： Bin Yu ,  Shibly Ahmed ,  Haihong Wang

IPC: H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A second device may be formed on the insulating layer, including a second fin. The second fin may be formed on the insulating layer and may have a second fin aspect ratio different from the first fin aspect ratio.

Abstract translation: 半导体器件可以包括衬底和形成在衬底上的绝缘层。 第一器件可以形成在绝缘层上，包括第一鳍片。 第一翅片可以形成在绝缘层上，并且可以具有第一翅片长宽比。 第二装置可以形成在绝缘层上，包括第二鳍片。 第二翅片可以形成在绝缘层上，并且可以具有与第一翅片长宽比不同的第二翅片长宽比。

公开(公告)号：US06852576B2

公开(公告)日：2005-02-08

申请号：US10825175

申请日：2004-04-16

Applicant: Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/786 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method forms fin structures for a semiconductor device. The method includes forming a first fin structure including a dielectric material and including a first side surface and a second side surface; forming a second fin structure adjacent the first side surface of the first fin structure; and forming a third fin structure adjacent the second side surface of the first fin structure. The second fin structure and the third fin structure are formed of a different material than the first fin structure.

Abstract translation: 一种形成半导体器件的鳍结构的方法。 该方法包括形成包括电介质材料并包括第一侧表面和第二侧表面的第一鳍结构; 在所述第一翅片结构的第一侧表面附近形成第二鳍结构; 以及在所述第一翅片结构的所述第二侧表面附近形成第三鳍​​结构。 第二翅片结构和第三翅片结构由与第一翅片结构不同的材料形成。

公开(公告)号：US06833588B2

公开(公告)日：2004-12-21

申请号：US10274867

申请日：2002-10-22

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

IPC: H01L2701

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66803

Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the gate is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin are surrounded by the gate. The gate material surrounding the fin has a U-shaped cross-section at a channel region of the semiconductor device.

公开(公告)号：US06706571B1

公开(公告)日：2004-03-16

申请号：US10274951

申请日：2002-10-22

Applicant: Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery ,  Haihong Wang

Inventor： Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery ,  Haihong Wang

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78684

Abstract: A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench. The film may then be etched, followed by an of the conductive layer to form the structures.

Abstract translation: 在半导体器件中形成多个结构的方法包括在导电层上沉积膜，蚀刻膜的一部分中的沟槽并且形成在沟槽的侧壁附近。 然后可以对该膜进行蚀刻，然后进行导电层的形成以形成结构。

公开(公告)号：US06611029B1

公开(公告)日：2003-08-26

申请号：US10290158

申请日：2002-11-08

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the subtrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces of the fin. A second gate and may be formed on the insulating layer separate from the first gate and proximate to another one of number of side surfaces of the fin.

Abstract translation: 半导体器件可以包括基板和形成在该副墨滴上的绝缘层。 鳍可以形成在绝缘层上，并且可以包括多个侧表面和顶表面。 第一栅极可以形成在靠近鳍片的多个侧表面中的一个的绝缘层上。 第二栅极，并且可以形成在与第一栅极分离并且靠近鳍片的多个侧表面中的另一个的绝缘层上。

公开(公告)号：US06448165B1

公开(公告)日：2002-09-10

申请号：US09746397

申请日：2000-12-21

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L213205

CPC classification number: H01L21/28123 ,  H01L21/32134 ,  Y10S977/707 ,  Y10S977/888 ,  Y10S977/891 ,  Y10S977/892

Abstract: For fabricating a field effect transistor within an active device area of a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate. A layer of gate electrode material is deposited on the layer of gate dielectric material, and the gate electrode material is a semiconductor material. At least one of an N-type dopant or a P-type dopant or a neutral dopant is implanted into the layer of gate electrode material such that the at least one of an N-type dopant or a P-type dopant or a neutral dopant has a dopant concentration in the layer of gate electrode material. A layer of photo-resist material, a layer of BARC (bottom anti-reflective coating) material, and the layer of gate electrode material are patterned to form a gate structure of the field effect transistor. The gate structure is comprised of the remaining gate electrode material, and the BARC (bottom anti-reflective coating) material remains on the gate structure. The BARC (bottom anti-reflective coating) material is then stripped from the gate structure using an etching reactant that etches both of the BARC (bottom anti-reflective coating) material and the gate electrode material. An etch rate of the gate electrode material in the etching reactant increases with an increase of the dopant concentration of the at least one of an N-type dopant or a P-type dopant or a neutral dopant within the gate electrode material. Sidewalls of the gate structure are trimmed by a trim length during the step of stripping the BARC (bottom anti-reflective coating) material from the gate structure. Thus, the dopant concentration of the at least one of an N-type dopant or a P-type dopant or a neutral dopant in the gate electrode material is adjusted to control the trim length of the gate structure.

Abstract translation: 为了在半导体衬底的有源器件区域内制造场效应晶体管，在半导体衬底上沉积一层栅介质材料。 栅极材料层沉积在栅极介电材料层上，栅电极材料是半导体材料。 N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种注入到栅电极材料层中，使得N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种 在栅极材料层中具有掺杂剂浓度。 将一层光致抗蚀剂材料，一层BARC（底部抗反射涂层）材料和该栅极电极材料层图案化以形成该场效应晶体管的栅极结构。 栅极结构由剩余的栅电极材料组成，并且BARC（底部抗反射涂层）材料保留在栅极结构上。 然后使用蚀刻BARC（底部抗反射涂层）材料和栅电极材料的蚀刻反应物，从栅极结构剥离BARC（底部抗反射涂层）材料。 蚀刻反应物中的栅电极材料的蚀刻速率随着栅极电极材料中的N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种的掺杂剂浓度的增加而增加。 在从栅极结构剥离BARC（底部抗反射涂层）材料的步骤期间，栅极结构的侧壁被修剪长度。 因此，调整栅电极材料中的N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种的掺杂剂浓度以控制栅极结构的修整长度。

公开(公告)号：US20120239778A1

公开(公告)日：2012-09-20

申请号：US13477999

申请日：2012-05-22

Applicant: Haihong Wang

Inventor： Haihong Wang

IPC: G06F15/16

CPC classification number: G06F17/30174 ,  Y10S707/99952

Abstract: Data replication includes generating replication data that is part of a replicated file system to be sent over a communication channel to a destination replication device; adding additional verification information to at least a portion of the replication data to prevent data corruption; and sending the replication data and the additional verification information over the communication channel to the destination replication device. The replication data with additional verification information is sent over the communication channel using a reliable protocol that allows the replication data to be verified by the reliable protocol at the destination replication device. The reliable protocol is a protocol capable of detecting most but not all data corruption introduced by the communication channel. The additional verification information includes information for verifying that replication data sent using the reliable protocol does not include data corruption that was introduced by the communication channel and undetected by the reliable protocol.

Abstract translation: 数据复制包括生成作为通过通信通道发送到目标复制设备的复制文件系统的一部分的复制数据; 向至少一部分复制数据添加其他验证信息，以防止数据损坏; 以及通过所述通信信道将所述复制数据和所述附加验证信息发送到所述目的地复制设备。 具有附加验证信息的复制数据通过通信通道使用可靠协议来发送，该协议允许复制数据由目的地复制设备上的可靠协议进行验证。 可靠的协议是能够检测通信信道引入的大多数但不是全部数据损坏的协议。 附加验证信息包括用于验证使用可靠协议发送的复制数据不包括由通信信道引入并且不被可靠协议检测到的数据损坏的信息。