公开(公告)号：US06911367B2

公开(公告)日：2005-06-28

申请号：US10418696

申请日：2003-04-18

申请人： Eric R. Blomiley ,  Er-Xuan Ping

发明人： Eric R. Blomiley ,  Er-Xuan Ping

IPC分类号： C30B25/02 ,  H01L21/205 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/20 ,  H01L21/36

CPC分类号： C30B29/06 ,  C30B25/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28512 ,  H01L21/28562 ,  H01L21/76 ,  H01L21/762 ,  H01L21/823481 ,  H01L29/66628 ,  H01L29/7834

摘要： The invention includes methods of forming epitaxially-grown semiconductive material having a flattened surface, and methods of incorporating such material into trenched regions and elevated/source drain regions. A method of forming epitaxially-grown semiconductive material having a flattened surface can include the following. Initially, a single crystal first semiconductor material is provided. A second semiconductive material is epitaxially grown from a surface of the first semiconductor material. The epitaxial growth is stopped, and subsequently an upper surface of the second semiconductor material is exposed to at least one hydrogen isotope to reduce curvature of (i.e., flatten) a surface of the second semiconductor material.

摘要翻译： 本发明包括形成具有平坦表面的外延生长的半导体材料的方法，以及将这种材料结合到沟槽区域和升高/源极漏极区域中的方法。 形成具有平坦表面的外延生长的半导体材料的方法可以包括以下。 首先，提供单晶第一半导体材料。 第二半导体材料从第一半导体材料的表面外延生长。 停止外延生长，随后将第二半导体材料的上表面暴露于至少一个氢同位素，以减小第二半导体材料的表面的曲率（即平坦化）。

公开(公告)号：US20050077595A1

公开(公告)日：2005-04-14

申请号：US10625952

申请日：2003-07-23

申请人： Ying Huang ,  Er-Xuan Ping

发明人： Ying Huang ,  Er-Xuan Ping

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/00

CPC分类号： H01L21/76844 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved method, structure and process flow for reducing line-line capacitance using low dielectric constant (K) materials is provided. Embodiments in accordance with the present invention form structures for semiconductor devices having a single level of interconnection as well as semiconductor devices having multiple levels of interconnection. In embodiments of the present invention, an initial dielectric structure is formed having a first low-K material overlaid with a standard-K material. In subsequent processing, conductive interconnects are formed and the standard-K material replaced with a second low-K material. In some embodiments of the present invention, the first and second low-K materials are the same material, in some embodiments the first and second low-K materials are different materials. Embodiments of the present invention having multiple levels of conductive interconnects are formed by employing methods and materials analogous to those used to form the first level of conductive interconnect and dielectric material disposed there between. Embodiments of the present invention employ low-K materials formed by spin-on processes as well as low-K materials formed by CVD processes.

摘要翻译： 提供了使用低介电常数（K）材料降低线路电容的改进方法，结构和工艺流程。 根据本发明的实施例形成具有单级互连的半导体器件的结构以及具有多个互连级别的半导体器件。 在本发明的实施例中，形成具有覆盖有标准K材料的第一低K材料的初始电介质结构。 在随后的处理中，形成导电互连，并用第二低K材料代替标准K材料。 在本发明的一些实施方案中，第一和第二低K材料是相同的材料，在一些实施方案中，第一和第二低K材料是不同的材料。 具有多层导电互连的本发明的实施例通过采用类似于用于形成第一级导电布线和介于其之间的介电材料的方法和材料而形成。 本发明的实施例采用通过旋涂工艺形成的低K材料以及通过CVD工艺形成的低K材料。

公开(公告)号：US06870210B2

公开(公告)日：2005-03-22

申请号：US10225428

申请日：2002-08-22

申请人： Er-Xuan Ping ,  Shenlin Chen

发明人： Er-Xuan Ping ,  Shenlin Chen

IPC分类号： H01G4/005 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/1085 ,  H01L27/10885 ,  H01L28/84 ,  H01L28/91

摘要： A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be optionally annealed to improve capacitance.

摘要翻译： 公开了双面HSG电容器和制造方法。 作为双面下电容器电极的一部分，在掺杂多晶层和半球状多晶硅层（HSG）之间形成薄的自然氧化物层。 在电介质形成之前，下部电容器电极可以任选退火以改善电容。

公开(公告)号：US06861326B2

公开(公告)日：2005-03-01

申请号：US09989931

申请日：2001-11-21

申请人： Fernando Gonzalez ,  Er-Xuan Ping

发明人： Fernando Gonzalez ,  Er-Xuan Ping

IPC分类号： H01L21/8242 ,  H01L21/84 ,  H01L27/12 ,  H01L21/331

CPC分类号： H01L27/10894 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/1203 ,  Y10S438/933

摘要： The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

摘要翻译： 本发明包括形成半导体电路的方法。 提供单晶硅衬底，并且形成覆盖衬底的第一部分并且留下未覆盖的第二部分的掩模。 在未覆盖部分中形成沟槽，并且至少部分地填充有半导体材料，该半导体材料包括除硅以外的元素的至少一个原子百分比。 去除掩模，并且在衬底的第一部分上形成第一半导体电路部件。 此外，第二半导体电路部件形成在至少部分地填充沟槽的半导体材料之上。 本发明还包括半导体结构。

公开(公告)号：US06704188B2

公开(公告)日：2004-03-09

申请号：US09922628

申请日：2001-08-06

申请人： Lingyi A. Zheng ,  Er-Xuan Ping

发明人： Lingyi A. Zheng ,  Er-Xuan Ping

IPC分类号： H01G4228

CPC分类号： H01L21/0217 ,  C23C16/0272 ,  C23C16/345 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31051 ,  H01L21/3115 ,  H01L21/3185 ,  H01L21/3211 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-containing substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-containing gas to desposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen-containing gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-containing substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.

摘要翻译： 提供了一种在半导体器件上形成氮化硅膜的方法。 在该方法的一个实施方案中，首先将含硅衬底暴露于二氯硅烷（DCS）和含氮气体的混合物，以将表面上的薄氮化硅接种层去除，然后暴露于四氯化硅 （TCS）和含氮气体以在DCS接种层上沉积TCS氮化硅层。 在另一个实施方案中，该方法包括在形成DCS氮化物接种层和TCS氮化物层之前首先氮化含硅衬底的表面。 该方法实现了具有足够厚度的TCS氮化物层，以消除起泡和穿通问题，并且不管衬底类型如何，都能提供高电性能。 还提供了形成电容器的方法以及所得到的电容器结构。

公开(公告)号：US06703268B2

公开(公告)日：2004-03-09

申请号：US10133029

申请日：2002-04-26

申请人： Er-Xuan Ping

发明人： Er-Xuan Ping

IPC分类号： H01L2100

CPC分类号： H01L21/02667 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/2022 ,  H01L29/66757 ,  H01L29/78675

摘要： A process to fabricate a thin film transistor using an intrinsic polycrystalline silicon film, by a method of: preparing a semiconductor assembly; forming an insulation layer on a substrate; forming a first amorphous silicon layer on said insulation layer; forming silicon nucleation sites on said first amorphous silicon layer; converting said first amorphous silicon layer into hemispherical grained silicon, said hemispherical grained silicon being formed about said silicon nucleation sites; forming a second amorphous silicon layer covering said hemispherical grained silicon; annealing said second amorphous silicon layer to convert said second amorphous silicon layer into a grained silicon film, said grained silicon film being formed about said hemispherical grained silicon and having a dimension of approximately 0.1 microns to 0.5 microns in size; patterning an oxide layer into a transistor gate oxide, thus leaving uncovered sections of said grained silicon on opposing sides of said transistor gate oxide; conductively doping said uncovered sections of said grained silicon; forming a patterned metal gate on said transistor gate oxide.

摘要翻译： 一种使用本征多晶硅膜制造薄膜晶体管的方法，通过以下方法：制备半导体组件; 在基板上形成绝缘层; 在所述绝缘层上形成第一非晶硅层; 在所述第一非晶硅层上形成硅成核位点; 将所述第一非晶硅层转变成半球形晶粒硅，所述半球形晶粒硅围绕所述硅成核位置形成; 形成覆盖所述半球形晶粒硅的第二非晶硅层; 对所述第二非晶硅层进行退火以将所述第二非晶硅层转化成晶粒硅膜，所述晶粒硅膜围绕所述半球形晶粒硅形成并具有约0.1微米至0.5微米尺寸的尺寸; 将氧化物层图案化成晶体管栅极氧化物，从而在所述晶体管栅极氧化物的相对侧上留下所述晶粒硅的未覆盖部分; 导电地掺杂所述粒状硅的所述未覆盖部分; 在所述晶体管栅极氧化物上形成图案化的金属栅极。

公开(公告)号：US06613628B2

公开(公告)日：2003-09-02

申请号：US09907680

申请日：2001-07-19

申请人： Lingyi A. Zheng ,  Er-Xuan Ping

发明人： Lingyi A. Zheng ,  Er-Xuan Ping

IPC分类号： H01L218242

CPC分类号： H01L28/40 ,  H01L27/0805 ,  H01L27/12 ,  H01L28/56 ,  H01L28/90

摘要： A method of forming a capacitor with reduced leakage current on a substrate in a semiconductor device is set forth. A first layer of a conductive material is formed over the substrate, and a second layer of a dielectric is formed over the first layer. The second layer is contacted with hydrogen, oxygen and nitrous oxide gases to form an oxidation layer over the second layer. A third layer of a conductive material is formed over the second layer to thereby form the capacitor. While the capacitor exhibits an improved leakage current reduction, overall capacitance is substantially unaffected, as compared to a similar capacitor having an oxidation layer built from a combination of oxygen and hydrogen gases only.

公开(公告)号：US06600207B2

公开(公告)日：2003-07-29

申请号：US10039456

申请日：2001-12-31

申请人： Ying Huang ,  Er-Xuan Ping

发明人： Ying Huang ,  Er-Xuan Ping

IPC分类号： H01L2900

CPC分类号： H01L21/76844 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure to reduce line—line capacitance using low dielectric constant (K) materials is provided. Embodiments in accordance with the present invention are semiconductor devices having a single level of interconnection as well as semiconductor devices having multiple levels of interconnection. In embodiments of the present invention, an initial dielectric structure has a first low-K material overlaid with a standard-K material. In subsequent processing, conductive interconnects are formed and the standard-K material replaced with a second low-K material. In some embodiments of the present invention, the first and second low-K materials are the same material, in some embodiments the first and second low-K materials are different materials. Embodiments of the present invention having multiple levels of conductive interconnects are formed by essentially repeating the method employed to form the first level of conductive interconnect. Embodiments of the present invention employ low-K materials formed by spin-on processes as well as low-K materials formed by CVD processes.

摘要翻译： 提供了一种使用低介电常数（K）材料降低线路电容的结构。 根据本发明的实施例是具有单级互连的半导体器件以及具有多级互连的半导体器件。 在本发明的实施例中，初始电介质结构具有覆盖有标准K材料的第一低K材料。 在随后的处理中，形成导电互连，并用第二低K材料代替标准K材料。 在本发明的一些实施方案中，第一和第二低K材料是相同的材料，在一些实施方案中，第一和第二低K材料是不同的材料。 通过基本上重复用于形成第一级导电互连的方法来形成具有多级导电互连的本发明的实施例。 本发明的实施例采用通过旋涂工艺形成的低K材料以及通过CVD工艺形成的低K材料。

公开(公告)号：US06509227B1

公开(公告)日：2003-01-21

申请号：US09503572

申请日：2000-02-14

申请人： Er-Xuan Ping ,  Randhir Thakur

发明人： Er-Xuan Ping ,  Randhir Thakur

IPC分类号： H01L218242

CPC分类号： H01L28/84 ,  C23C16/24 ,  C23C16/56 ,  Y10S438/964

摘要： The present invention provides methods of forming in situ doped rugged silicon and semiconductor devices incorporating conductive rugged silicon. In one aspect, the methods involve forming a layer of doped amorphous silicon on a substrate at a substantially constant deposition temperature; and converting the amorphous silicon layer into hemispherical grain silicon by annealing the amorphous silicon layer at substantially the deposition temperature while varying pressure. In another aspect, the methods involve forming a discontinuous first layer of doped silicon on a substrate; forming a second layer of amorphous silicon on the first layer of doped silicon and the substrate not covered by the first layer of doped silicon; and annealing the first and second layers. In yet another aspect, the methods involve forming a discontinuous first layer of silicon on a substrate and forming a second conformal layer of doped amorphous silicon on the first layer of doped silicon.

公开(公告)号：US06498063B1

公开(公告)日：2002-12-24

申请号：US09975879

申请日：2001-10-12

申请人： Er-Xuan Ping

发明人： Er-Xuan Ping

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L21/3185 ,  H01L27/10817 ,  H01L28/75 ,  H01L28/84 ,  H01L28/90 ,  H01L28/91

摘要： A method of providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semiconductor assembly having both nitridation receptive and resistive materials. For purposes of the present invention, a nitride-nucleation enhancing monolayer is a material that will readily accept the bonding of nitrogen atoms to the material itself. Next, a silicon nitride layer is formed over the nonconductive nitride-nucleation enhancing monolayer. The nonconductive nitride-nucleation enhancing monolayer provides even nucleation over both the nitridation receptive material and the nitridation resistive material for silicon nitride, thereby allowing for the growth of a uniformly thin nitride layer.

摘要翻译： 在硅和氧化物表面之间提供均匀成核的方法，用于生长半导体器件中使用的均匀薄的氮化硅层。 首先，在具有氮化接受和电阻材料的半导体组件上形成非导电氮化物成核增强单层。 为了本发明的目的，氮化物成核增强单层是容易接受氮原子结合到材料本身的材料。 接下来，在非导电氮化物成核增强单层上形成氮化硅层。 非导电氮化物成核增强单层在氮化接触材料和用于氮化硅的氮化电阻材料两者上均匀成核，从而允许生长均匀的氮化物薄层。