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    Method, structure and process flow to reduce line-line capacitance with low-K material
    1.
    发明授权
    Method, structure and process flow to reduce line-line capacitance with low-K material 有权
    方法，结构和工艺流程，以低K材料降低线路电容

    公开(公告)号：US06919638B2

    公开(公告)日：2005-07-19

    申请号：US10625952

    申请日：2003-07-23

    申请人： Ying Huang ,  Er-Xuan Ping

    发明人： Ying Huang ,  Er-Xuan Ping

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/04

    CPC分类号： H01L21/76844 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An improved method, structure and process flow for reducing line-line capacitance using low dielectric constant (K) materials is provided. Embodiments in accordance with the present invention form structures for semiconductor devices having a single level of interconnection as well as semiconductor devices having multiple levels of interconnection. In embodiments of the present invention, an initial dielectric structure is formed having a first low-K material overlaid with a standard-K material. In subsequent processing, conductive interconnects are formed and the standard-K material replaced with a second low-K material. In some embodiments of the present invention, the first and second low-K materials are the same material, in some embodiments the first and second low-K materials are different materials. Embodiments of the present invention having multiple levels of conductive interconnects are formed by employing methods and materials analogous to those used to form the first level of conductive interconnect and dielectric material disposed there between. Embodiments of the present invention employ low-K materials formed by spin-on processes as well as low-K materials formed by CVD processes.

    摘要翻译： 提供了使用低介电常数（K）材料降低线路电容的改进方法，结构和工艺流程。 根据本发明的实施例形成具有单级互连的半导体器件的结构以及具有多个互连级别的半导体器件。 在本发明的实施例中，形成具有覆盖有标准K材料的第一低K材料的初始电介质结构。 在随后的处理中，形成导电互连，并用第二低K材料代替标准K材料。 在本发明的一些实施方案中，第一和第二低K材料是相同的材料，在一些实施方案中，第一和第二低K材料是不同的材料。 具有多层导电互连的本发明的实施例通过采用类似于用于形成第一级导电布线和介于其之间的介电材料的方法和材料而形成。 本发明的实施例采用通过旋涂工艺形成的低K材料以及通过CVD工艺形成的低K材料。

    An improved method, structure and process flow to reduce line-line capacitance with low-K material
    2.
    发明申请
    An improved method, structure and process flow to reduce line-line capacitance with low-K material 有权
    改进的方法，结构和工艺流程，以减少低K材料的线路电容

    公开(公告)号：US20050077595A1

    公开(公告)日：2005-04-14

    申请号：US10625952

    申请日：2003-07-23

    申请人： Ying Huang ,  Er-Xuan Ping

    发明人： Ying Huang ,  Er-Xuan Ping

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/00

    CPC分类号： H01L21/76844 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An improved method, structure and process flow for reducing line-line capacitance using low dielectric constant (K) materials is provided. Embodiments in accordance with the present invention form structures for semiconductor devices having a single level of interconnection as well as semiconductor devices having multiple levels of interconnection. In embodiments of the present invention, an initial dielectric structure is formed having a first low-K material overlaid with a standard-K material. In subsequent processing, conductive interconnects are formed and the standard-K material replaced with a second low-K material. In some embodiments of the present invention, the first and second low-K materials are the same material, in some embodiments the first and second low-K materials are different materials. Embodiments of the present invention having multiple levels of conductive interconnects are formed by employing methods and materials analogous to those used to form the first level of conductive interconnect and dielectric material disposed there between. Embodiments of the present invention employ low-K materials formed by spin-on processes as well as low-K materials formed by CVD processes.

    摘要翻译： 提供了使用低介电常数（K）材料降低线路电容的改进方法，结构和工艺流程。 根据本发明的实施例形成具有单级互连的半导体器件的结构以及具有多个互连级别的半导体器件。 在本发明的实施例中，形成具有覆盖有标准K材料的第一低K材料的初始电介质结构。 在随后的处理中，形成导电互连，并用第二低K材料代替标准K材料。 在本发明的一些实施方案中，第一和第二低K材料是相同的材料，在一些实施方案中，第一和第二低K材料是不同的材料。 具有多层导电互连的本发明的实施例通过采用类似于用于形成第一级导电布线和介于其之间的介电材料的方法和材料而形成。 本发明的实施例采用通过旋涂工艺形成的低K材料以及通过CVD工艺形成的低K材料。

    Structure to reduce line-line capacitance with low K material
    3.
    发明授权
    Structure to reduce line-line capacitance with low K material 有权
    结构以低K材料降低线路电容

    公开(公告)号：US06600207B2

    公开(公告)日：2003-07-29

    申请号：US10039456

    申请日：2001-12-31

    申请人： Ying Huang ,  Er-Xuan Ping

    发明人： Ying Huang ,  Er-Xuan Ping

    IPC分类号： H01L2900

    CPC分类号： H01L21/76844 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure to reduce line—line capacitance using low dielectric constant (K) materials is provided. Embodiments in accordance with the present invention are semiconductor devices having a single level of interconnection as well as semiconductor devices having multiple levels of interconnection. In embodiments of the present invention, an initial dielectric structure has a first low-K material overlaid with a standard-K material. In subsequent processing, conductive interconnects are formed and the standard-K material replaced with a second low-K material. In some embodiments of the present invention, the first and second low-K materials are the same material, in some embodiments the first and second low-K materials are different materials. Embodiments of the present invention having multiple levels of conductive interconnects are formed by essentially repeating the method employed to form the first level of conductive interconnect. Embodiments of the present invention employ low-K materials formed by spin-on processes as well as low-K materials formed by CVD processes.

    摘要翻译： 提供了一种使用低介电常数（K）材料降低线路电容的结构。 根据本发明的实施例是具有单级互连的半导体器件以及具有多级互连的半导体器件。 在本发明的实施例中，初始电介质结构具有覆盖有标准K材料的第一低K材料。 在随后的处理中，形成导电互连，并用第二低K材料代替标准K材料。 在本发明的一些实施方案中，第一和第二低K材料是相同的材料，在一些实施方案中，第一和第二低K材料是不同的材料。 通过基本上重复用于形成第一级导电互连的方法来形成具有多级导电互连的本发明的实施例。 本发明的实施例采用通过旋涂工艺形成的低K材料以及通过CVD工艺形成的低K材料。

    Method, structure and process flow to reduce line-line capacitance with low-K material
    4.
    发明申请
    Method, structure and process flow to reduce line-line capacitance with low-K material 审中-公开

    公开(公告)号：US20050006775A1

    公开(公告)日：2005-01-13

    申请号：US10912921

    申请日：2004-08-06

    申请人： Ying Huang ,  Er-Xuan Ping

    发明人： Ying Huang ,  Er-Xuan Ping

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763 ,  H01L29/40

    CPC分类号： H01L21/76844 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An improved method, structure and process flow for reducing line-line capacitance using low dielectric constant (K) materials is provided. Embodiments in accordance with the present invention form structures for semiconductor devices having a single level of interconnection as well as semiconductor devices having multiple levels of interconnection. In embodiments of the present invention, an initial dielectric structure is formed having a first low-K material overlaid with a standard-K material. In subsequent processing, conductive interconnects are formed and the standard-K material replaced with a second low-K material. In some embodiments of the present invention, the first and second low-K materials are the same material, in some embodiments the first and second low-K materials are different materials. Embodiments of the present invention having multiple levels of conductive interconnects are formed by employing methods and materials analogous to those used to form the first level of conductive interconnect and dielectric material disposed there between. Embodiments of the present invention employ low-K materials formed by spin-on processes as well as low-K materials formed by CVD processes.

    Method, structure and process flow to reduce line-line capacitance with low-K material
    5.
    发明授权
    Method, structure and process flow to reduce line-line capacitance with low-K material 有权
    方法，结构和工艺流程，以低K材料降低线路电容

    公开(公告)号：US06531407B1

    公开(公告)日：2003-03-11

    申请号：US09653153

    申请日：2000-08-31

    申请人： Ying Huang ,  Er-Xuan Ping

    发明人： Ying Huang ,  Er-Xuan Ping

    IPC分类号： H01L2131

    CPC分类号： H01L21/76844 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An improved method, structure and process flow for reducing line-line capacitance using low dielectric constant (K) materials is provided. Embodiments in accordance with the present invention form structures for semiconductor devices having a single level of interconnection as well as semiconductor devices having multiple levels of interconnection. In embodiments of the present invention, an initial dielectric structure is formed having a first low-K material overlaid with a standard-K material. In subsequent processing, conductive interconnects are formed and the standard-K material replaced with a second low-K material. In some embodiments of the present invention, the first and-second low-K materials are the same material, in some embodiments the first and second low-K materials are different materials. Embodiments of the present invention having multiple levels of conductive interconnects are formed by employing methods and materials analogous to those used to form the first level of conductive interconnect and dielectric material disposed there between. Embodiments of the present invention employ low-K materials formed by spin-on processes as well as low-K materials formed by CVD processes.

    摘要翻译： 提供了使用低介电常数（K）材料降低线路电容的改进方法，结构和工艺流程。 根据本发明的实施例形成具有单级互连的半导体器件的结构以及具有多个互连级别的半导体器件。 在本发明的实施例中，形成具有覆盖有标准K材料的第一低K材料的初始电介质结构。 在随后的处理中，形成导电互连，并用第二低K材料代替标准K材料。 在本发明的一些实施方案中，第一和第二低K材料是相同的材料，在一些实施方案中，第一和第二低K材料是不同的材料。 具有多层导电互连的本发明的实施例通过采用类似于用于形成第一级导电布线和介于其之间的介电材料的方法和材料而形成。 本发明的实施例采用通过旋涂工艺形成的低K材料以及通过CVD工艺形成的低K材料。

    Reduction of shorts among electrical cells formed on a semiconductor substrate
    6.
    发明授权
    Reduction of shorts among electrical cells formed on a semiconductor substrate 有权
    减少在半导体衬底上形成的电池之间的短路

    公开(公告)号：US06399983B1

    公开(公告)日：2002-06-04

    申请号：US09389294

    申请日：1999-09-02

    申请人： Er-Xuan Ping ,  Ying Huang

    发明人： Er-Xuan Ping ,  Ying Huang

    IPC分类号： H01L218242

    CPC分类号： H01L28/91 ,  H01L28/84

    摘要： An integrated circuit, such as a DRAM circuit, having a plurality of cells is formed in containers formed an isolation layer positioned on an first surface of a semiconductor substrate. The containers have a first region located proximal the first surface of the semiconductor substrate that has a first cross-sectional area and a second region located distal from the first surface of the semiconductor substrate that has a second cross-sectional area that is less than the first cross-sectional area. Cells, such as capacitors, are formed in the containers and the isolation material positioned between adjacent cells is removed so that a generally horizontal surface is formed. The horizontal surface is located closer to the first surface of the substrate than the transition between the first region and the second region of the container so that substantially vertical surfaces are formed in the isolation region linking the cells to the horizontal surface of the isolation layer. The addition of the vertical surfaces on the isolation region increases the surface path upon which leakage current will flow between adjacent cells thereby decreasing the likelihood of leakage currents travelling from one cell to an adjacent cell.

    摘要翻译： 具有多个单电池的诸如DRAM电路的集成电路形成在形成在半导体衬底的第一表面上的隔离层的容器中。 这些容器具有位于半导体衬底的第一表面附近的第一区域，该第一区域具有第一横截面区域和位于远离半导体衬底的第一表面的第二区域，第二区域的第二横截面积小于 第一个横截面积。 在容器中形成诸如电容器的电池，并且移除位于相邻电池之间的隔离材料，从而形成大致水平的表面。 水平表面比容器的第一区域和第二区域之间的过渡位置更靠近基板的第一表面，使得在将单元连接到隔离层的水平表面的隔离区域中形成基本垂直的表面。 在隔离区域上添加垂直表面增加了在相邻单元之间泄漏电流将流过的表面路径，从而降低了漏电流从一个单元行进到相邻单元的可能性。

    DIODES WITH NATIVE OXIDE REGIONS FOR USE IN MEMORY ARRAYS AND METHODS OF FORMING THE SAME
    10.
    发明申请
    DIODES WITH NATIVE OXIDE REGIONS FOR USE IN MEMORY ARRAYS AND METHODS OF FORMING THE SAME 有权
    具有用于存储器阵列的内部氧化物区域的二极体及其形成方法

    公开(公告)号：US20120193756A1

    公开(公告)日：2012-08-02

    申请号：US13020007

    申请日：2011-02-02

    申请人： Steven Maxwell ,  Abhijit Bandyopadhyay ,  Kun Hou ,  Er-Xuan Ping ,  Yung-Tin Chen ,  Li Xiao

    发明人： Steven Maxwell ,  Abhijit Bandyopadhyay ,  Kun Hou ,  Er-Xuan Ping ,  Yung-Tin Chen ,  Li Xiao

    IPC分类号： H01L29/861 ,  H01L21/36 ,  H01L29/92

    CPC分类号： H01L27/1021 ,  H01L29/868 ,  Y10S438/90

    摘要： In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供一种垂直半导体二极管，其包括：（1）形成在基板上的第一半导体层; （2）形成在第一半导体层上方的第二半导体层; （3）形成在所述第一半导体层上方的第一自然氧化物层; 以及（4）形成在第一半导体层上的第三半导体层，第二半导体层和第一自然氧化物层，以形成包括第一自然氧化物层的垂直半导体二极管。 提供了许多其他方面。