公开(公告)号：US20110156145A1

公开(公告)日：2011-06-30

申请号：US13042973

申请日：2011-03-08

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

IPC分类号： H01L29/78

CPC分类号： H01L29/42392 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S438/926 ,  Y10S438/957

摘要： A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

摘要翻译： 描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。 离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许在沟道区下方除去氧化物。 一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。

公开(公告)号：US20110115028A1

公开(公告)日：2011-05-19

申请号：US13013942

申请日：2011-01-26

申请人： Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Brian S. Doyle

发明人： Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Brian S. Doyle

IPC分类号： H01L27/092

CPC分类号： H01L21/28079 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

摘要： In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.

摘要翻译： 在金属栅极替换工艺中，可以在NMOS和PMOS晶体管的沟道中选择性地诱发应变。 例如，可以使用具有比衬底更高的热膨胀系数的材料来形成PMOS晶体管的栅电极。 可以使用具有比基板的热膨胀系数更低的热膨胀系数的材料来形成NMOS晶体管的栅电极。

公开(公告)号：US20110079837A1

公开(公告)日：2011-04-07

申请号：US12967238

申请日：2010-12-14

申请人： Brian S. Doyle ,  Robert S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

发明人： Brian S. Doyle ,  Robert S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L29/785

摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

摘要翻译： 电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。 第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。 第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。 第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。 在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

公开(公告)号：US07898041B2

公开(公告)日：2011-03-01

申请号：US11855823

申请日：2007-09-14

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

IPC分类号： H01L27/01

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858

摘要： A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

摘要翻译： 一种用于纳米尺度通道器件的接触结构，其具有耦合到具有多个平行半导体器件的器件的源极或漏极区域之间并具有接触结构的接触结构。 接触结构能够接触具有亚光刻间距的平行半导体本体。

公开(公告)号：US07898023B2

公开(公告)日：2011-03-01

申请号：US12826954

申请日：2010-06-30

申请人： Brian S. Doyle ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Robert S. Chau

发明人： Brian S. Doyle ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Robert S. Chau

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L29/66545 ,  H01L29/66795

摘要： Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

摘要翻译： 通常描述嵌入式沟道阵列晶体管（RCAT）结构和形成方法。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的第一鳍，第一鳍包括第一源极区和第一漏极区，以及形成凹陷沟道阵列晶体管（RCAT）的第一栅极结构 在设置在第一源极区域和第一漏极区域之间的第一栅极区域中，其中通过去除牺牲栅极结构以暴露第一栅极区域中的第一鳍片而形成第一栅极结构，将沟道结构凹入第一鳍片， 以及在所述凹陷通道结构上形成所述第一栅极结构。

公开(公告)号：US07820513B2

公开(公告)日：2010-10-26

申请号：US12259464

申请日：2008-10-28

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。

公开(公告)号：US20100200917A1

公开(公告)日：2010-08-12

申请号：US12767681

申请日：2010-04-26

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

摘要翻译： 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

公开(公告)号：US20090206405A1

公开(公告)日：2009-08-20

申请号：US12032594

申请日：2008-02-15

申请人： Brian S. Doyle ,  Ravi Pillarisetty ,  Robert S. Chau

发明人： Brian S. Doyle ,  Ravi Pillarisetty ,  Robert S. Chau

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/517 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/785

摘要： Fin field-effect-transistor (finFET) structures having two dielectric thicknesses are generally described. In one example, an apparatus includes a semiconductor substrate, a semiconductor fin coupled with the semiconductor substrate, the semiconductor fin having at least a first surface, a second surface, and a third surface, the third surface being substantially parallel to the first surface and substantially perpendicular to the second surface, a spacer dielectric coupled to the second surface of the semiconductor fin, a back gate dielectric having a back gate dielectric thickness coupled to the first surface of the semiconductor fin, and a front gate dielectric having a front gate dielectric thickness coupled to the third surface of the semiconductor fin wherein the back gate dielectric thickness is greater than the front gate dielectric thickness

摘要翻译： 通常描述具有两个介电厚度的鳍场效应晶体管（finFET）结构。 在一个示例中，装置包括半导体衬底，与半导体衬底耦合的半导体鳍片，半导体鳍片具有至少第一表面，第二表面和第三表面，第三表面基本上平行于第一表面， 基本上垂直于第二表面的隔离电介质，耦合到半导体鳍片的第二表面的间隔电介质，具有耦合到半导体鳍片的第一表面的背栅电介质厚度的背栅电介质和具有前栅极电介质 耦合到半导体鳍片的第三表面的厚度，其中背栅电介质厚度大于前栅极电介质厚度

公开(公告)号：US20090166743A1

公开(公告)日：2009-07-02

申请号：US11964633

申请日：2007-12-26

申请人： Ravi Pillarisetty ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L29/785

摘要： Independent gate electrodes for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) gate stacks coupled with the semiconductor fin, the one or more PD gate stacks including a PD gate electrode, and one or more multi-gate pass gate (PG) gate stacks coupled with the semiconductor fin, the one or more PG gate stacks including a PG gate electrode, the PG gate electrode having a greater threshold voltage than the PD gate electrode.

摘要翻译： 通常描述用于多栅极晶体管的独立栅电极。 在一个示例中，装置包括半导体鳍片，与半导体鳍片耦合的一个或多个多栅极下拉（PD）栅极叠层，所述一个或多个PD栅极堆叠包括PD栅极电极和一个或多个多栅极 所述PG栅极堆叠与所述半导体鳍片耦合，所述一个或多个PG栅极堆叠包括PG栅极电极，所述PG栅电极具有比所述PD栅电极更大的阈值电压。

公开(公告)号：US07547637B2

公开(公告)日：2009-06-16

申请号：US11158661

申请日：2005-06-21

申请人： Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

发明人： Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau ,  Brian S. Doyle

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

摘要翻译： 对半导体膜的图案化方法进行说明。 根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密 并且其中所述硬掩模形成在所述第二晶体平面上。 接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。 然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。