公开(公告)号：US08058706B2

公开(公告)日：2011-11-15

申请号：US12555646

申请日：2009-09-08

申请人： Chien-Te Feng ,  Kazuaki Ano ,  Frank Yu ,  Trevor Liu

发明人： Chien-Te Feng ,  Kazuaki Ano ,  Frank Yu ,  Trevor Liu

IPC分类号： H01L29/06

CPC分类号： H01L29/0657 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29035 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48475 ,  H01L2224/4848 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85051 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10156 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/35121 ,  Y10T29/49128 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ≧5% less than a cross sectional area of the top surface to provide a protruding lip having a bottom lip surface. A package substrate includes a top substrate surface including substrate bonding sites, a bottom substrate surface, and a die support structure on the top substrate surface having a gap region. The bottom lip surface of the IC die is secured to the die support structure and the bottom surface of the IC die extends below the die support structure into the gap region. Coupling connectors couple the bonding features on the IC die to the substrate bonding sites.

摘要翻译： 封装的电子器件包括厚度形状的IC管芯，其包括顶部，顶面，有源电路，底部和底面。 底面的横截面积比顶面的截面积小5％以提供具有底唇表面的突出唇缘。 封装衬底包括顶部衬底表面，其包括衬底结合部位，底部衬底表面以及具有间隙区域的顶部衬底表面上的管芯支撑结构。 IC芯片的底部唇表面固定到模具支撑结构，并且IC芯片的底表面在模具支撑结构的下方延伸到间隙区域中。 耦合连接器将IC芯片上的结合特征耦合到基板结合位置。

公开(公告)号：US08037234B2

公开(公告)日：2011-10-11

申请号：US12252155

申请日：2008-10-15

申请人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma

发明人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0246 ,  G06F3/0607 ,  G06F3/0632 ,  G06F12/0607 ,  G06F2212/1036 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C13/0004

摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

摘要翻译： 闪存模块具有通过NVM控制器通过物理块地址（PBA）总线访问的原始NAND闪存芯片。 NVM控制器位于闪存模块或固态硬盘（SSD）的系统板上。 NVM控制器将逻辑块地址（LBA）转换为物理块地址（PBA）。 闪存模块的多个通道之间的数据条带化和交织由智能存储事务管理器控制在高电平，而在信道内的进一步的交织和重新映射可由NVM控制器执行。 智能存储交换机使用SDRAM缓冲区，在写入闪存之前缓存主机数据。 Q-R指针表存储主机地址的商和余数。 剩余部分指向SDRAM中主机数据的位置。 命令队列存储主机命令的Q，R。

公开(公告)号：US20110066837A1

公开(公告)日：2011-03-17

申请号：US12947211

申请日：2010-11-16

申请人： Charles C. Lee ,  Abraham C. Ma ,  Frank Yu ,  Shimon Chen

发明人： Charles C. Lee ,  Abraham C. Ma ,  Frank Yu ,  Shimon Chen

IPC分类号： G06F15/177 ,  G06F12/02 ,  G06F13/28 ,  G06F9/24

CPC分类号： G06F9/4401 ,  G06F13/387 ,  G06F2213/3854

摘要： A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues.

摘要翻译： 多媒体卡（MMC）单片闪存器件（SCFD）包含一个MMC闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 初始引导加载程序由状态机从闪存的第一页读取并写入小RAM。 微控制器中的中央处理单元（CPU）从小型RAM读取指令，执行初始启动加载程序，从Flash读取更多的页面。 这些页面被小RAM缓冲并写入较大的DRAM。 一旦将扩展引导顺序写入DRAM，CPU将切换一个RAM_BASE位，以使DRAM从DRAM获取指令。 然后从DRAM执行扩展启动顺序，将OS映像从闪存复制到DRAM。 引导代码和控制代码在代码更新操作期间被有选择地覆盖以消除存货问题。

公开(公告)号：US20110016267A1

公开(公告)日：2011-01-20

申请号：US12887477

申请日：2010-09-21

申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

IPC分类号： G06F12/08 ,  G06F13/28

CPC分类号： G06F13/28 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30 ,  Y02D10/14

摘要： A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams.

摘要翻译： 闪存卡读卡器通过使用多个管道的批量流传输来提高传输效率。 批量数据输出管道将主机写入数据传送到读卡器，并且可以与承载从附接到读卡器的闪存卡读取的主机读取数据的批量数据输入管并行操作。 状态数据包不会阻塞数据包，因为状态数据包通过单独的状态管道进行缓冲，命令通过命令管道缓冲。 来自多个闪存卡的闪存数据被交织为共享大容量数据管道的单独端点。 数据输入/输出流状态机通过批量数据输入和数据输出管道控制流批量数据，而状态流状态机通过状态管道控制流状态数据包。 使用批量流量减少事务开销，其中几个命令的数据包被组合成相同的批量流。

公开(公告)号：US20100275037A1

公开(公告)日：2010-10-28

申请号：US12831160

申请日：2010-07-06

申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma ,  Jim Chin-Nan Ni ,  Shimon Chen

发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma ,  Jim Chin-Nan Ni ,  Shimon Chen

IPC分类号： G06F13/36 ,  G06F13/10 ,  G06F1/04 ,  G06F13/28 ,  H04L9/00 ,  G06F1/32

CPC分类号： G06F13/385 ,  G11C16/102 ,  G11C2216/30 ,  Y02D10/14 ,  Y02D10/151

摘要： A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices.

摘要翻译： 低功耗闪存设备使用修改后的通用串行总线（USB）3.0协议来降低功耗。 当应用程序中的USB电缆长度短时，位时钟减慢了功率，并且需要预加重。 通过消除8/10位编码器并将同步和成帧字节编码为9位符号来提高数据效率。 数据字节只有在数据中出现一系列6个数据字节时才能通过位填充进行扩展。 标头和有效载荷数据以每个数据字节近8位的形式传输，而成帧是每个符号9位，远远小于每个字节的标准10位。 使用低功率链路层，物理层和缩小协议层。 读卡器转换器集线器允许USB主机访问低功耗USB设备。 只有一个闪存设备被访问，与标准的USB广播相比，将功耗降低到多个设备。

公开(公告)号：US20090236715A1

公开(公告)日：2009-09-24

申请号：US12050722

申请日：2008-03-18

申请人： Kazuaki Ano ,  Frank Yu ,  Wei Lung Hsu

发明人： Kazuaki Ano ,  Frank Yu ,  Wei Lung Hsu

IPC分类号： H01L23/00 ,  H01L21/50

CPC分类号： H01L24/83 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32057 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83855 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3025

摘要： The invention relates to microelectronic semiconductor chip assemblies having vertically stacked layers. In a disclosed example of a preferred embodiment, a vertically stacked semiconductor chip assembly includes a first semiconductor chip affixed to the surface of a substrate. A laminated interposing layer therebetween includes a first adhesive material and a second adhesive material, at least one of the adhesive materials adapted to capturing debris. Methods are disclosed for making a vertically stacked semiconductor chip assemblies by joining first and second adhesive materials to form a laminated interposing layer between a first chip and second chip or substrate. In preferred embodiments of the invention, the interposing layer includes polyimide film and one adhesive material of relatively low elasticity, and another adhesive material having relatively high elasticity.

摘要翻译： 本发明涉及具有垂直堆叠层的微电子半导体芯片组件。 在优选实施例的公开示例中，垂直堆叠的半导体芯片组件包括固定到基板表面的第一半导体芯片。 其间的层叠中介层包括第一粘合材料和第二粘合材料，至少一种粘合剂材料适于捕获碎片。 公开了通过接合第一和第二粘合剂材料来形成垂直堆叠的半导体芯片组件以在第一芯片和第二芯片或衬底之间形成层叠的中介层的方法。 在本发明的优选实施例中，插入层包括聚酰亚胺膜和一种弹性相对较低的粘合材料，另一种粘合材料具有较高的弹性。

公开(公告)号：US20090204872A1

公开(公告)日：2009-08-13

申请号：US12427675

申请日：2009-04-21

申请人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma

发明人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma

IPC分类号： G06F12/08 ,  G06F12/02 ,  H03M13/05 ,  G06F11/10

CPC分类号： G06F12/0246 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0607 ,  G06F12/0804 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C7/00 ,  G11C11/5621 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/0483

摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

公开(公告)号：US08543742B2

公开(公告)日：2013-09-24

申请号：US13494409

申请日：2012-06-12

申请人： Frank Yu ,  Abraham C. Ma ,  Shimon Chen

发明人： Frank Yu ,  Abraham C. Ma ,  Shimon Chen

IPC分类号： G06F13/28 ,  G06F3/00 ,  G06F11/00

CPC分类号： G06F13/28 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0688 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0607 ,  G06F13/385 ,  G06F2212/7208 ,  G06F2212/7211 ,  G06F2213/3802

摘要： A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches.

摘要翻译： 智能闪存驱动器具有一个或多个级别的智能存储交换机和较低级别的单芯片闪存设备（SCFD）。 SCFD包含执行低级坏块映射和磨损均衡以及逻辑到物理块映射的闪存和控制器。 SCFD向上游智能存储交换机报告其容量，布置和最大磨损级数（WLC）和坏块号（BBN），将该信息存储在结构寄存器中。 智能存储交换机选择具有最大BBN作为目标的SCFD，而当WLC超过随时间上升的阈值时，具有最低最大WLC的SCFD作为用于损耗均衡的交换的来源。 顶级智能存储交换机从低级智能存储交换机接收统一的容量，安排，WLC和BBN信息。 数据是条带化的，并且可选地由所有级别的智能存储交换机中的冗余冗余阵列（RAID）控制器加扰。

公开(公告)号：US08321597B2

公开(公告)日：2012-11-27

申请号：US13197721

申请日：2011-08-03

申请人： Frank Yu ,  Abraham C. Ma ,  Shimon Chen

发明人： Frank Yu ,  Abraham C. Ma ,  Shimon Chen

IPC分类号： G06F13/28 ,  G06F9/00

CPC分类号： G06F13/28 ,  G06F3/0658 ,  G06F3/0679 ,  G06F11/108 ,  G06F12/0246 ,  G06F13/385 ,  G06F21/79 ,  G06F2212/7208 ,  G06F2212/7211

摘要： A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches.

摘要翻译： 智能闪存驱动器具有一个或多个级别的智能存储交换机和较低级别的单芯片闪存设备（SCFD）。 SCFD包含执行低级坏块映射和磨损均衡以及逻辑到物理块映射的闪存和控制器。 SCFD向上游智能存储交换机报告其容量，布置和最大磨损级数（WLC）和坏块号（BBN），将该信息存储在结构寄存器中。 智能存储交换机选择具有最大BBN作为目标的SCFD，并且具有最低最大WLC的SCFD作为WLC超过随时间上升的阈值时的损耗平衡的交换源。 顶级智能存储交换机从低级智能存储交换机接收统一的容量，安排，WLC和BBN信息。 数据是条带化的，并且可选地由所有级别的智能存储交换机中的冗余冗余阵列（RAID）控制器加扰。

公开(公告)号：US08200862B2

公开(公告)日：2012-06-12

申请号：US12887477

申请日：2010-09-21

申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

IPC分类号： G06F13/12 ,  G06F13/00 ,  G06F12/02

CPC分类号： G06F13/28 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30 ,  Y02D10/14

摘要： A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams.

摘要翻译： 闪存卡读卡器通过使用多个管道的批量流传输来提高传输效率。 批量数据输出管道将主机写入数据传送到读卡器，并且可以与承载从附接到读卡器的闪存卡读取的主机读取数据的批量数据输入管并行操作。 状态数据包不会阻塞数据包，因为状态数据包通过单独的状态管道进行缓冲，命令通过命令管道缓冲。 来自多个闪存卡的闪存数据被交织为共享大容量数据管道的单独端点。 数据输入/输出流状态机通过批量数据输入和数据输出管道控制流批量数据，而状态流状态机通过状态管道控制流状态数据包。 使用批量流量减少事务开销，其中几个命令的数据包被组合成相同的批量流。