ELECTRODE FOR HIGH PEFORMANCE Li-ION BATTERIES
    63.
    发明申请
    ELECTRODE FOR HIGH PEFORMANCE Li-ION BATTERIES 审中-公开
    高效锂离子电池电极

    公开(公告)号:US20110200881A1

    公开(公告)日:2011-08-18

    申请号:US13023425

    申请日:2011-02-08

    IPC分类号: H01M4/485 H01M4/26 B05D5/12

    摘要: A method for forming an electrode for a battery is disclosed. The method includes providing a substrate. A plurality of clusters of lithium containing compound is formed over the substrate, with each cluster having a plurality of sub-structures of lithium containing compound that exhibit nanocrystalline structure. The plurality of sub-structures of lithium containing compound are transformed to exhibit cation ordering structure. In some embodiments, a protective layer is disposed over the cluster of Li containing compound. An electrode for a battery and a system for processing the substrate are also disclosed.

    摘要翻译: 公开了一种形成电池用电极的方法。 该方法包括提供基板。 在衬底上形成多个含锂化合物簇,每个簇具有多个呈现纳米晶体结构的含锂化合物的子结构。 将含锂化合物的多个子结构转化为阳离子排序结构。 在一些实施方案中,保护层设置在含锂化合物的簇上。 还公开了一种用于电池的电极和用于处理衬底的系统。

    METROLOGY METHODS AND APPARATUS FOR NANOMATERIAL CHARACTERIZATION OF ENERGY STORAGE ELECTRODE STRUCTURES
    66.
    发明申请
    METROLOGY METHODS AND APPARATUS FOR NANOMATERIAL CHARACTERIZATION OF ENERGY STORAGE ELECTRODE STRUCTURES 失效
    能量储存电极结构的纳米材料特征的计量方法和装置

    公开(公告)号:US20100200403A1

    公开(公告)日:2010-08-12

    申请号:US12368105

    申请日:2009-02-09

    IPC分类号: C25D15/02 C25B11/10

    摘要: Embodiments described herein generally relate to methods and apparatus for forming an electrode structure used in an energy storage device. More particularly, embodiments described herein relate to methods and apparatus for characterizing nanomaterials used in forming high capacity electrode structures for energy storage devices. In one embodiment a process for forming an electrode structure for an energy storage device is provided. The process comprises depositing a columnar metal structure over a substrate at a first current density by a diffusion limited deposition process, measuring a capacitance of the columnar metal structure to determine a surface area of the columnar metal structure, and depositing three dimensional porous metal structures over the columnar metal structure at a second current density greater than the first current density.

    摘要翻译: 本文描述的实施例一般涉及用于形成在能量存储装置中使用的电极结构的方法和装置。 更具体地,本文描述的实施例涉及用于形成用于形成能量存储装置的高容量电极结构的纳米材料的方法和装置。 在一个实施例中,提供了一种用于形成用于能量存储装置的电极结构的方法。 该方法包括通过扩散限制沉积工艺在第一电流密度的衬底上沉积柱状金属结构,测量柱状金属结构的电容以确定柱状金属结构的表面积,并将三维多孔金属结构沉积在 所述柱状金属结构的第二电流密度大于所述第一电流密度。

    POROUS THREE DIMENSIONAL COPPER, TIN, COPPER-TIN, COPPER-TIN-COBALT, AND COPPER-TIN-COBALT-TITANIUM ELECTRODES FOR BATTERIES AND ULTRA CAPACITORS
    67.
    发明申请
    POROUS THREE DIMENSIONAL COPPER, TIN, COPPER-TIN, COPPER-TIN-COBALT, AND COPPER-TIN-COBALT-TITANIUM ELECTRODES FOR BATTERIES AND ULTRA CAPACITORS 失效
    电池和超电容器的多孔三维铜,锡,铜箔,铜 - 钴和铜 - 钴 - 钛电极

    公开(公告)号:US20100193365A1

    公开(公告)日:2010-08-05

    申请号:US12696422

    申请日:2010-01-29

    IPC分类号: C25D5/00 C25D17/00

    摘要: A method and apparatus for forming a reliable and cost efficient battery or electrochemical capacitor electrode structure that has an improved lifetime, lower production costs, and improved process performance are provided. In one embodiment a method for forming a three dimensional porous electrode for a battery or an electrochemical cell is provided. The method comprises depositing a columnar metal layer over a substrate at a first current density by a diffusion limited deposition process and depositing three dimensional metal porous dendritic structures over the columnar metal layer at a second current density greater than the first current density.

    摘要翻译: 提供了一种形成可靠且具有成本效益的电池或电化学电容器电极结构的方法和装置,其具有改善的寿命,降低生产成本和改进的工艺性能。 在一个实施例中,提供了一种用于形成用于电池或电化学电池的三维多孔电极的方法。 该方法包括通过扩散限制沉积工艺以第一电流密度在衬底上沉积柱状金属层,并以大于第一电流密度的第二电流密度在柱状金属层上沉积三维金属多孔树枝状结构。

    Silver under-layers for electroless cobalt alloys
    68.
    发明授权
    Silver under-layers for electroless cobalt alloys 有权
    无电钴合金的银层

    公开(公告)号:US07064065B2

    公开(公告)日:2006-06-20

    申请号:US10967101

    申请日:2004-10-15

    IPC分类号: H01L21/44 C23C28/02 C25D3/46

    摘要: In one embodiment, a method for depositing a capping layer on a substrate surface containing a copper layer is provided which includes exposing the substrate surface to a zinc solution, exposing the substrate surface to a silver solution to form a silver layer thereon and depositing the capping layer on the silver layer by an electroless deposition process. A second silver layer may be formed on the capping layer, if desired. In another embodiment, a composition of a deposition solution useful for forming a cobalt tungsten alloy contains calcium tungstate, a cobalt source at a concentration within a range from about 50 mM to about 500 mM, a complexing agent at a concentration within a range from about 100 mM to about 700 mM, and a buffering agent at a concentration within a range from about 50 mM to about 500 mM.

    摘要翻译: 在一个实施例中,提供了一种用于在包含铜层的衬底表面上沉积覆盖层的方法,其包括将衬底表面暴露于锌溶液,将衬底表面暴露于银溶液以在其上形成银层并沉积封盖 通过无电镀沉积工艺在银层上。 如果需要,可以在覆盖层上形成第二银层。 在另一个实施方案中,可用于形成钴钨合金的沉积溶液的组合物含有钨酸钙,浓度在约50mM至约500mM范围内的钴源,浓度在约 100mM至约700mM的缓冲剂和浓度为约50mM至约500mM的缓冲剂。

    Manufacturing seedless barrier layers in integrated circuits
    70.
    发明授权
    Manufacturing seedless barrier layers in integrated circuits 有权
    在集成电路中制造无核屏障层

    公开(公告)号:US06893955B1

    公开(公告)日:2005-05-17

    申请号:US10328347

    申请日:2002-12-24

    IPC分类号: H01L23/532 H01L21/4763

    摘要: An integrated circuit manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seedless barrier layer lines the opening, and a conductor core fills the opening over the seedless barrier layer. The barrier layer is deposited in the opening and contains atomic layers of barrier material which bonds to the dielectric layer, an intermediate material which bonds to the barrier material layer and to the conductor core, and a conductor core material which bonds to the intermediate material. The conductor core bonds to the conductor core material.

    摘要翻译: 提供了具有半导体器件的半导体衬底的集成电路制造方法。 在半导体衬底上形成器件电介质层,器件电介质层上的沟道电介质层上形成有开口。 阻挡层对通道开口进行排列,并且导体芯填充阻挡层上的开口。 无核屏障层对开口进行排列,并且导体芯填充无核阻挡层上的开口。 阻挡层沉积在开口中并且包含键合到电介质层的阻挡材料的原子层,结合到阻挡材料层和导体芯的中间材料以及与中间材料结合的导体芯材料。 导体芯与导体芯材料结合。