公开(公告)号：US06319834B1

公开(公告)日：2001-11-20

申请号：US09639812

申请日：2000-08-17

申请人： Darrell M. Erb ,  Steven C. Avanzino ,  Fei Wang

发明人： Darrell M. Erb ,  Steven C. Avanzino ,  Fei Wang

IPC分类号： H01L2144

CPC分类号： H01L21/3212 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76879

摘要： A pattern of in-laid conductors is formed by a method utilizing electroplating and chemical-mechanical polishing (CMP). Embodiments include a first step of selectively filling recesses formed in the surface of a substrate with a metal by localized electroplating at a reduced thickness, planar-surfaced overburden or blanket layer thereon, and planarizing the surface by CMP utilizing a relatively soft CMP pad. Embodiments also include an apparatus comprising a porous pad applicator for selectively electroplating recesses formed in the surface of a workpiece.

摘要翻译： 通过使用电镀和化学机械抛光（CMP）的方法形成嵌入导体的图案。 实施例包括第一步骤，通过局部电镀在其上以薄的局部电镀，平面表面覆盖层或覆盖层选择性地填充形成在衬底的表面中的凹陷，并且通过使用相对较软的CMP衬垫的CMP来平坦化表面。 实施例还包括一种包括用于选择性地电镀在工件表面中形成的凹槽的多孔垫施加器的装置。

公开(公告)号：US06291339B1

公开(公告)日：2001-09-18

申请号：US09225218

申请日：1999-01-04

申请人： Steven C. Avanzino ,  Simon S. Chan

发明人： Steven C. Avanzino ,  Simon S. Chan

IPC分类号： H01L214263

CPC分类号： H01L21/76819

摘要： A bilayer interlayer dielectric having a spun-on low k gap filled layer is capped with a higher k dielectric layer. Prior to the capping, the spun-on low k dielectric layer is planarized to reduce or eliminate the systematic variation in the relative thickness of the layers due to pattern density effects on the thickness of the spun-on low k dielectric layer. By removing the variations in the relative thickness of the low k dielectric layer and the capping layer, the effective dielectric constant of the uniformly thick composite interlayer dielectric is independent of location on the circuit, preventing differences in circuit speed and the creation of clock skew in the circuit.

摘要翻译： 具有旋转低k间隙填充层的双层层间电介质用较高的k电介质层封装。 在封盖之前，由于图案密度对纺丝低k电介质层的厚度的影响，使旋转低k电介质层平坦化以减少或消除层的相对厚度的系统变化。 通过去除低k电介质层和覆盖层的相对厚度的变化，均匀厚的复合层间电介质的有效介电常数与电路上的位置无关，防止电路速度的差异和时钟偏差的产生 电路。

公开(公告)号：US06235453B1

公开(公告)日：2001-05-22

申请号：US09349055

申请日：1999-07-07

申请人： Lu You ,  Steven C. Avanzino ,  Jacques Bertrand ,  Richard J. Huang

发明人： Lu You ,  Steven C. Avanzino ,  Jacques Bertrand ,  Richard J. Huang

IPC分类号： G03F726

CPC分类号： G03F7/427 ,  G03F7/42 ,  H01L21/02052 ,  H01L21/31138

摘要： An integrated circuit and a method of removing photoresist is described. The process described uses a low oxygen gas or non-oxygen gas plasma that removes the photoresist and provides a protective surface layer over the low-k dielectric material. The low-k dielectric material is part of a dielectric stack. After exposure to the gas plasmas the integrated circuit is subjected to solvent.

摘要翻译： 描述了集成电路和去除光致抗蚀剂的方法。 所描述的方法使用低氧气体或非氧气体等离子体，其去除光致抗蚀剂并在低k电介质材料上提供保护性表面层。 低k电介质材料是电介质叠层的一部分。 暴露于气体等离子体后，集成电路经受溶剂。

公开(公告)号：US06232635B1

公开(公告)日：2001-05-15

申请号：US09543991

申请日：2000-04-06

申请人： Larry Yu Wang ,  Steven C. Avanzino ,  Jeffrey A. Shields ,  Stephen Keetai Park

发明人： Larry Yu Wang ,  Steven C. Avanzino ,  Jeffrey A. Shields ,  Stephen Keetai Park

IPC分类号： H01L291788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.

摘要翻译： 制造半导体闪存单元的制品和方法。 该方法包括在硅衬底上制造隔离层，在隔离层上形成氧化物，在其上生长隧道氧化物层，沉积第一多晶硅层，掩蔽和蚀刻第一多晶硅层，沉积第二多晶硅 层并进行覆盖层回蚀步骤，形成形成第三多晶硅层的氧化物/氮化物/氧化物层并在其上沉积硅化物层。

公开(公告)号：US06211071B1

公开(公告)日：2001-04-03

申请号：US09296552

申请日：1999-04-22

申请人： Todd P. Lukanc ,  Fei Wang ,  Steven C. Avanzino

发明人： Todd P. Lukanc ,  Fei Wang ,  Steven C. Avanzino

IPC分类号： H01L214763

CPC分类号： H01L21/76873 ,  H01L21/2885 ,  H01L21/31133 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877

摘要： In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improve reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments include preventing “pinching-off” of the recess opening due to overhanging nucleation/seed layer deposits at the corners of the opening as a result of localized increased rates of deposition. Further embodiments include providing a dual-layered dielectric layer comprising different dielectric materials and performing a first, isotropic etching process of the upper lamina of the dielectric layer for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, followed by a second, anisotropic etching process for extending the recess at a substantially constant width for a predetermined depth into the lower lamina of the dielectric layer. The tapered width profile of the recess effectively prevents formation of overhanging deposits thereat which can result in occlusion and void formation during electroplating for filling the recesses.

摘要翻译： 在电介质层的表面形成例如铜或铜合金的成网金属化图案，通过电镀无孔地填充形成在电介质层表面的凹槽，从而显着提高可靠性。 实施例包括由于局部增加的沉积速率而导致由于在开口的角部处的悬垂成核/种子层沉积而导致的凹陷开口的“夹断”。 另外的实施例包括提供包括不同介电材料的双层电介质层，并执行电介质层的上层的第一，各向同性蚀刻工艺，用于选择性地使凹口开口的宽度变窄，以在衬底表面提供更宽的开口， 随后进行第二种各向异性蚀刻工艺，用于将凹槽以基本上恒定的宽度延伸到介电层的下层中的预定深度。 凹陷的锥形宽度轮廓有效地防止了在其中形成悬垂沉积物，这可能导致电镀期间的闭塞和空隙形成以填充凹部。

公开(公告)号：US06184141B2

公开(公告)日：2001-02-06

申请号：US09198369

申请日：1998-11-24

申请人： Steven C. Avanzino ,  Kashmir S. Sahota ,  Gerd Marxsen

发明人： Steven C. Avanzino ,  Kashmir S. Sahota ,  Gerd Marxsen

IPC分类号： H01L2100

CPC分类号： H01L21/3212

摘要： A method of planarizing a copper containing conductive layer of a semiconductor wafer forms a blanketing copper containing layer within and upon a patterned substrate layer. Chemical mechanical polish (CMP) planarizing is performed on the copper containing layer at a relatively fast rate of removal until most of the layer is removed. The remaining portion of the layer is then CMP planarized at a second rate of removal, which is slower than the first rate of removal, until the copper containing layer is substantially completely removed and a barrier layer underlying the copper containing layer is reached. The multiple phase planarization of the copper containing layer avoids excessive dishing and pattern erosion while maintaining high throughput and uniform removal.

摘要翻译： 平面化半导体晶片的含铜导电层的方法在图案化的衬底层的内部和之上形成覆盖铜的层。 化学机械抛光（CMP）平面化在含铜层上以相对较快的去除速率进行，直到大部分层被去除。 然后将层的剩余部分以第二除去速率平坦化，其比第一脱除速率慢，直到基本上完全除去含铜层，并且到达含铜层下面的阻挡层。 含铜层的多相平面化避免了过度的凹陷和图案侵蚀，同时保持了高产量和均匀的去除。

公开(公告)号：US6117782A

公开(公告)日：2000-09-12

申请号：US296556

申请日：1999-04-22

申请人： Todd P. Lukanc ,  Fei Wang ,  Steven C. Avanzino

发明人： Todd P. Lukanc ,  Fei Wang ,  Steven C. Avanzino

IPC分类号： H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76873 ,  H01L21/76804 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7688

摘要： In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improved reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments include preventing "pinching-off" of the recess opening due overhanging nucleation/seed layer deposits at the corners of the opening as a result of localized increased rates of deposition. Embodiments also include providing a dual-layered dielectric layer comprising different dielectric materials and performing a first, isotropic etching process of the upper (sacrificial) lamina of the dielectric layer for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, followed by a second, anisotropic etching process for extending the recess at a substantially constant width for a predetermined depth into the lower lamina of the dielectric layer. The tapered width profile of the recess effectively prevents formation of overhanging deposits thereat which can result in occlusion and void formation during electroplating for filling the recesses. After electroplating, the recess-filled, plated surface is subjected to planarization processing, as by CMP, wherein the entire thickness of the second, upper lamina of the dielectric layer is removed.

摘要翻译： 在电介质层的表面上形成例如铜或铜合金的嵌入式金属化图案，通过电镀无孔地填充在电介质层表面中形成的凹槽，从而显着提高了可靠性。 实施例包括由于局部增加的沉积速率，在开口的角部处由于突出的成核/种子层沉积而阻止凹口的“夹断”。 实施例还包括提供包括不同电介质材料的双层电介质层，并且执行电介质层的上（牺牲）层的第一，各向同性蚀刻工艺，用于选择性地使凹口开口的宽度变窄，从而在 衬底表面，随后进行第二种各向异性蚀刻工艺，用于以基本上恒定的宽度将凹槽延伸到介电层的下层中的预定深度。 凹陷的锥形宽度轮廓有效地防止了在其中形成悬垂沉积物，这可能导致电镀期间的闭塞和空隙形成以填充凹部。 在电镀之后，通过CMP对凹陷填充的镀覆表面进行平坦化处理，其中去除介电层的第二上层的整个厚度。

公开(公告)号：US4954459A

公开(公告)日：1990-09-04

申请号：US376176

申请日：1989-07-03

申请人： Steven C. Avanzino ,  Jacob D. Haskell

发明人： Steven C. Avanzino ,  Jacob D. Haskell

IPC分类号： H01L21/76 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/762

CPC分类号： H01L21/3212 ,  H01L21/31056 ,  H01L21/76229 ,  Y10S148/051 ,  Y10S438/959

摘要： A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: depositing, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of the integrated circuit structure; forming a patterned mask layer over said deposited oxide layer with one or more openings therein in registry with the higher height first portions of the integrated circuit structure; etching exposed portions of said conformal oxide layer through the mask openings down to a level approximately equal to the level of the unexposed portion of the conformal oxide layer; removing the mask layer; and polishing the oxide layer to remove raised portions of the conformal oxide layer remaining after the etching step to form a highly planarized structure. Optionally, the oxide layer may be further etched anisotropically until the upper surfaces of the underlying integrated circuit structure is exposed.

摘要翻译： 公开了一种用于制造具有平坦化到集成电路结构的相邻部分的平面的沉积氧化物部分的高度平坦化的集成电路结构的方法，其包括：在集成电路结构上沉积，该集成电路结构具有高于其余部分的高度的第一部分 集成电路结构，具有超过所述集成电路结构的其余部分之上的所述第一部分的高度的厚度的共形氧化物层; 在其上具有一个或多个开口的所述沉积的氧化物层上形成图案化掩模层，与所述集成电路结构的较高高度的第一部分对齐; 将所述保形氧化物层的暴露部分通过所述掩模开口蚀刻到约等于所述共形氧化物层的未曝光部分的水平的水平; 去除掩模层; 并抛光氧化物层以除去在蚀刻步骤之后残留的保形氧化物层的凸起部分，以形成高度平坦化的结构。 任选地，可以进一步各向异性地蚀刻氧化物层，直到暴露底层集成电路结构的上表面。

公开(公告)号：US07084062B1

公开(公告)日：2006-08-01

申请号：US11033653

申请日：2005-01-12

申请人： Steven C. Avanzino ,  Amit P. Marathe

发明人： Steven C. Avanzino ,  Amit P. Marathe

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76852 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/146 ,  H01L45/16

摘要： Disclosed are methods for deposition of improved memory element films for semiconductor devices. The methods involve providing a hard mask over an upper surface of a metal line of a semiconductor substrate where vias are to be placed, recess etching the mask substantially in all upper surfaces except where vias are to be placed, depositing a Ta-containing capping layer over substantially all the metal line surfaces except the surface where vias are to be placed, polishing the Ta-containing capping layer to produce a damascened Ta-containing cap while exposing the metal line at the via forming surface, depositing a dielectric layer, patterning the dielectric layer to form a via to expose a portion of the metal line, and depositing memory element films. The improved Ta—Cu interface of the subject invention mitigates and/or eliminates lateral growth of memory element films and copper voiding under the dielectric layer at the top surface of the metal line, and thereby enhances reliability and performance of semiconductor devices.

摘要翻译： 公开了用于沉积用于半导体器件的改进的存储元件膜的方法。 所述方法包括在要放置通孔的半导体衬底的金属线的上表面上提供硬掩模，基本上在除了要放置通孔之外的所有上表面中蚀刻掩模，沉积含Ta的覆盖层 在除了要放置通孔的表面之外的基本上所有的金属线表面上，抛光含Ta的封盖层，以在露出金属线在通孔形成表面的同时产生一个镶嵌的含Ta盖，沉积介电层， 电介质层以形成通孔以暴露金属线的一部分，以及沉积存储元件膜。 本发明的改进的Ta-Cu界面缓和了和/或消除了金属线顶表面下的介质层下存储元件膜的横向生长和铜空隙化，从而提高了半导体器件的可靠性和性能。

公开(公告)号：US06841473B1

公开(公告)日：2005-01-11

申请号：US10672126

申请日：2003-09-26

申请人： Pin-Chin Connie Wang ,  Steven C. Avanzino

发明人： Pin-Chin Connie Wang ,  Steven C. Avanzino

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76862 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.

摘要翻译： 提供了一种具有半导体器件的半导体衬底的集成电路的制造方法。 形成在半导体衬底上的器件电介质层。 器件电介质层上的沟道电介质层具有形成在其中的开口。 屏障层对通道开口进行排列。 导体芯填充阻挡层上的开口。 铈导体互连帽设置在导电芯上方，在电介质层和铈导体互连帽上方具有覆盖层。