公开(公告)号：US09105741B2

公开(公告)日：2015-08-11

申请号：US13614062

申请日：2012-09-13

申请人： Kevin K. Chan ,  Jinghong Li ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Qingyun Yang

发明人： Kevin K. Chan ,  Jinghong Li ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Qingyun Yang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/7848

摘要： A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.

摘要翻译： 形成半导体结构的方法可以包括形成至少一个翅片并且在所述至少一个翅片结构的第一部分上形成栅极。 栅极间隔物可以形成在栅极的侧壁上，由此间隔物的形成产生与该至少一个鳍片的侧壁相邻的凹陷区域。 形成第一外延区域，其覆盖所述凹陷区域中的一个和所述至少一个翅片的第二部分，使得所述第二部分从所述栅极间隔物之一向外延伸。 通过蚀刻第一外延区域和至少一个鳍片的第二部分，在一个凹陷区域内形成第一外延层。 第二外延区域形成在相邻一个间隔物的位置和在一个凹陷区域内的第一外延层上方。

公开(公告)号：US09099585B2

公开(公告)日：2015-08-04

申请号：US13605068

申请日：2012-09-06

申请人： Bahman Hekmatshoar-Tabari ,  Marinus Hopstaken ,  Dae-Gyu Park ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Bahman Hekmatshoar-Tabari ,  Marinus Hopstaken ,  Dae-Gyu Park ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/0216 ,  H01L31/0376 ,  H01L31/075 ,  H01L31/18 ,  H01L31/20

CPC分类号： H01L31/03762 ,  H01L31/02167 ,  H01L31/075 ,  H01L31/1864 ,  H01L31/202 ,  Y02E10/548 ,  Y02P70/521

摘要： A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.

摘要翻译： 一种形成光电器件的半导体材料的方法，该方法包括提供含氢化非晶硅的材料的表面，以及在含氘气氛中对含氢化非晶硅的材料进行退火。 来自含氘气体的氘通过含氢化非晶硅材料的表面被引入到含氢化非晶硅材料的晶格中。 在一些实施方案中，引入含氢可氢化非晶硅的晶格的晶格的氘增加了含氢化非晶硅的材料的稳定性。

公开(公告)号：US20140070316A1

公开(公告)日：2014-03-13

申请号：US13614062

申请日：2012-09-13

申请人： Kevin K. Chan ,  Jinghong Li ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Qingyun Yang

发明人： Kevin K. Chan ,  Jinghong Li ,  Dae-Gyu Park ,  Xinhui Wang ,  Yun-Yu Wang ,  Qingyun Yang

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/7848

摘要： A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.

摘要翻译： 形成半导体结构的方法可以包括形成至少一个翅片并且在所述至少一个翅片结构的第一部分上形成栅极。 栅极间隔物可以形成在栅极的侧壁上，由此间隔物的形成产生与该至少一个鳍片的侧壁相邻的凹陷区域。 形成第一外延区域，其覆盖所述凹陷区域中的一个和所述至少一个翅片的第二部分，使得所述第二部分从所述栅极间隔物之一向外延伸。 通过蚀刻第一外延区域和至少一个鳍片的第二部分，在一个凹陷区域内形成第一外延层。 第二外延区域形成在相邻一个间隔物的位置和在一个凹陷区域内的第一外延层上方。

公开(公告)号：US08637381B2

公开(公告)日：2014-01-28

申请号：US13274381

申请日：2011-10-17

申请人： Effendi Leobandung ,  Dae-Gyu Park ,  Shom S. Ponoth ,  Zhibin Ren ,  Ghavam G. Shahidi ,  Leathen Shi

发明人： Effendi Leobandung ,  Dae-Gyu Park ,  Shom S. Ponoth ,  Zhibin Ren ,  Ghavam G. Shahidi ,  Leathen Shi

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L27/12 ,  H01L21/762 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/76251 ,  H01L29/78603

摘要： Aspects of the invention provide for preventing undercuts during wafer etch processing and enhancing back-gate to channel electrical coupling. In one embodiment, aspects of the invention include a semiconductor structure, including: a high-k buried oxide (BOX) layer atop a bulk silicon wafer, the high-k BOX layer including: at least one silicon nitride layer; and a high-k dielectric layer; and a silicon-on-insulator (SOI) layer positioned atop the high-k BOX layer.

摘要翻译： 本发明的各方面提供了在晶片蚀刻处理期间防止底切并且增强了后栅极到沟道电耦合。 在一个实施例中，本发明的方面包括半导体结构，包括：高体积硅晶片顶部的高k掩埋氧化物（BOX）层，高k BOX层包括：至少一个氮化硅层; 和高k电介质层; 以及位于高k BOX层顶上的绝缘体上硅（SOI）层。

公开(公告)号：US08557670B1

公开(公告)日：2013-10-15

申请号：US13605253

申请日：2012-09-06

申请人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Tak H. Ning ,  Dae-Gyu Park

发明人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Tak H. Ning ,  Dae-Gyu Park

IPC分类号： H01L21/8222

CPC分类号： H01L29/42304 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7371

摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.

摘要翻译： 在绝缘体上半导体衬底上形成横向异质结双极晶体管，该衬底包括具有第一带隙和第一导电类型掺杂的第一半导体材料的顶部半导体部分。 形成外部基座和基座的堆叠，使得叠层跨越顶部半导体部分。 在堆叠周围形成介电隔离件。 执行第二导电类型的掺杂剂的离子注入以掺杂未被叠层和电介质间隔物掩蔽的顶部半导体部分的区域，由此形成发射极区域和集电极区域。 具有大于第一带隙的第二带隙并且具有第二导电类型的掺杂的第二半导体材料被选择性地沉积在发射极区域和集电极区域上，以分别形成发射极接触区域和集电极接触区域。

公开(公告)号：US20130256757A1

公开(公告)日：2013-10-03

申请号：US13433537

申请日：2012-03-29

申请人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Tak H. Ning ,  Dae-Gyu Park

发明人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Tak H. Ning ,  Dae-Gyu Park

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/42304 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7371

摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.

摘要翻译： 在绝缘体上半导体衬底上形成横向异质结双极晶体管，该衬底包括具有第一带隙和第一导电类型掺杂的第一半导体材料的顶部半导体部分。 形成外部基座和基座的堆叠，使得叠层跨越顶部半导体部分。 在堆叠周围形成介电隔离件。 执行第二导电类型的掺杂剂的离子注入以掺杂未被叠层和电介质间隔物掩蔽的顶部半导体部分的区域，由此形成发射极区域和集电极区域。 具有大于第一带隙的第二带隙并且具有第二导电类型的掺杂的第二半导体材料被选择性地沉积在发射极区域和集电极区域上，以分别形成发射极接触区域和集电极接触区域。

公开(公告)号：US20120301706A1

公开(公告)日：2012-11-29

申请号：US13568808

申请日：2012-08-07

申请人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

发明人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

IPC分类号： C23C16/50 ,  B32B3/26

CPC分类号： C23C16/45536 ,  C23C16/36 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/3141 ,  H01L21/3148 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76831 ,  Y10T428/24999

摘要： A method of depositing a SiNxCy liner on a porous low thermal conductivity (low-k) substrate by plasma-enhanced atomic layer deposition (PE-ALD), which includes forming a SiNxCy liner on a surface of a low-k substrate having pores on a surface thereon, in which the low-k substrate is repeatedly exposed to a aminosilane-based precursor and a plasma selected from nitrogen, hydrogen, oxygen, helium, and combinations thereof until a thickness of the liner is obtained, and wherein the liner is prevented from penetrating inside the pores of a surface of the substrate. A porous low thermal conductivity substrate having a SiNxCy liner formed thereon by the method is also disclosed.

摘要翻译： 一种通过等离子体增强原子层沉积（PE-ALD）在多孔低热导率（低k）衬底上沉积SiNxCy衬垫的方法，其包括在具有孔的低k衬底的表面上形成SiN xCy衬垫 其中低k衬底反复暴露于基于氨基硅烷的前体和选自氮，氢，氧，氦及其组合的等离子体，直到获得衬垫的厚度，并且其中衬垫是 防止在基板的表面的孔内渗透。 还公开了通过该方法在其上形成SiN xCy衬垫的多孔低热导率衬底。

公开(公告)号：US08299535B2

公开(公告)日：2012-10-30

申请号：US12823163

申请日：2010-06-25

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

摘要翻译： 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括从底部到顶部的第一外延掺杂半导体材料的第一层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变;第二层 位于第一层顶部的第二外延掺杂半导体材料和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角形单层的上表面上的金属半导体合金触点。

公开(公告)号：US20120261717A1

公开(公告)日：2012-10-18

申请号：US13533499

申请日：2012-06-26

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L27/092

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.

摘要翻译： 公开了包括位于半导体衬底上的至少一个FET栅叠层的半导体结构。 所述至少一个FET栅极堆叠包括位于半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 嵌入式应力元件位于至少一个FET栅极堆叠的相对侧并且位于半导体衬底内。 每个应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，以及第二外延掺杂半导体材料的上层。 至少一个单层的掺杂剂位于每个嵌入的应力元件的上层内。

公开(公告)号：US20110316044A1

公开(公告)日：2011-12-29

申请号：US12823163

申请日：2010-06-25

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

摘要翻译： 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括从底部到顶部的第一外延掺杂半导体材料的第一层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变;第二层 位于第一层顶部的第二外延掺杂半导体材料和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角形单层的上表面上的金属半导体合金触点。