公开(公告)号：US07245027B2

公开(公告)日：2007-07-17

申请号：US10823858

申请日：2004-04-14

申请人： Chang-Ho Lee ,  Jong-Hyun Choi

发明人： Chang-Ho Lee ,  Jong-Hyun Choi

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/14

摘要： A device and method for layout and fabrication of power supply bus lines in an integrated circuit such as a memory circuit are described. In accordance with the present invention, power bus lines and bonding pads of the circuit are not necessarily formed in both edge regions and center regions of the device. The bonding pads are formed in the region according to the package being used, and the power bus lines are formed in the other region. This is accomplished by forming the bonding pads over landing pads. Landing pads are formed in both the center region and the edge region under the top surface of the device. If the device is to be packaged in an edge pad configuration, the bonding pads are formed over the landing pads in the edge region, and power supply bus lines can be formed over the landing pads in the center region. Similarly, if the device is to be packaged in a center pad configuration, the bonding pads are formed over the landing pads in the center region, and the power supply bus lines can be formed over the landing pads in the edge region. The bonding pads are connected to the landing pads by conductive vias. Because the power bus lines are not formed in the same region as bonding pads, they can occupy a relatively large portion of the region in which they are formed. That is, they can be made much larger than they would be using the conventional approach in which both bonding pads and power bus lines are formed in the same region. As a result, the power noise drawbacks of the conventional approach are eliminated.

公开(公告)号：US20070153614A1

公开(公告)日：2007-07-05

申请号：US11711615

申请日：2007-02-28

申请人： Seouk-Kyu Choi ,  Nam-Jong Kim ,  Il-Man Bae ,  Jong-Hyun Choi

发明人： Seouk-Kyu Choi ,  Nam-Jong Kim ,  Il-Man Bae ,  Jong-Hyun Choi

IPC分类号： G11C5/14

CPC分类号： G11C11/4085 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2207/2227

摘要： In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

摘要翻译： 在一个示例性实施例中，速度电路路径包括根据半导体器件的工作模式，可控制的工作在较慢的，低亚阈值泄漏电流模式或更快，更高的亚阈值泄漏电流模式的逆变器链。 非速度电路路径包括用于减小子阈值泄漏电流的逆变器链，而与半导体器件的工作模式无关。

公开(公告)号：US20070098042A1

公开(公告)日：2007-05-03

申请号：US11482448

申请日：2006-07-07

申请人： Jong-Hyun Choi ,  Dong-Il Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo

IPC分类号： G01K7/00

CPC分类号： G01K7/015 ,  G01K2219/00

摘要： A temperature detecting circuit is provided. The temperature detecting circuit includes a reference and detection voltage generator for generating a reference voltage corresponding to a first and a second reference current, and changing first to M-th (M being a natural number) detection currents based on first to M-th temperature detection codes to generate first to M-th detection voltages corresponding to the changed first to M-th detection currents and the second reference current; a temperature detection signal generator for comparing each of the first to M-th detection voltages with the reference voltage to generate first to M-th temperature detection signals; and a temperature detection controller for detecting an operation temperature of a semiconductor device while changing the first to M-th temperature detection codes in response to the first to M-th temperature detection signals from the temperature detection signal generator.

摘要翻译： 提供温度检测电路。 温度检测电路包括用于产生对应于第一和第二参考电流的参考电压的参考和检测电压发生器，并且基于第一至第M温度首先改变为第M（M为自然数）检测电流 检测码，用于产生对应于改变的第一至第M检测电流和第二参考电流的第一至第M检测电压; 温度检测信号发生器，用于将第一至第M检测电压中的每一个与参考电压进行比较，以产生第一至第M温度检测信号; 以及温度检测控制器，用于响应于来自温度检测信号发生器的第一至第M温度检测信号，在改变第一至第M温度检测代码的同时检测半导体器件的工作温度。

公开(公告)号：US20060286780A1

公开(公告)日：2006-12-21

申请号：US10570285

申请日：2004-09-02

申请人： Jin Jang ,  Jong-Hyun Choi ,  Seung-Soo Kim ,  Jae-Hwan Oh ,  Jun-Hyuk Chon

发明人： Jin Jang ,  Jong-Hyun Choi ,  Seung-Soo Kim ,  Jae-Hwan Oh ,  Jun-Hyuk Chon

IPC分类号： H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/02425 ,  H01L21/02488 ,  H01L21/02672 ,  H01L27/1277 ,  H01L29/78603

摘要： Disclosed are a method for forming a silicon thin-film on a substrate, and more particularly a method for forming a polycrystalline silicon thin-film of good quality on a flexible metal substrate. A metal substrate (110) is prepared and a surface of the metal substrate (110) is flattened. An insulation film (120) formed on the metal substrate (110). An amorphous silicon layer (130) is formed on the insulation film (120). A metal layer (140) is formed on the amorphous silicon layer (130). A sample on the metal substrate (110) is heated and crystallized.

摘要翻译： 公开了一种在基板上形成硅薄膜的方法，更具体地说，涉及一种在柔性金属基板上形成质量好的多晶硅薄膜的方法。 准备金属基板（110），使金属基板（110）的表面变平。 形成在金属基板（110）上的绝缘膜（120）。 在绝缘膜（120）上形成非晶硅层（130）。 金属层（140）形成在非晶硅层（130）上。 将金属基板（110）上的样品加热并结晶。

公开(公告)号：US20060023519A1

公开(公告)日：2006-02-02

申请号：US11005023

申请日：2004-12-07

申请人： Seouk-Kyu Choi ,  Nam-Jong Kim ,  Il-Man Bae ,  Jong-Hyun Choi

发明人： Seouk-Kyu Choi ,  Nam-Jong Kim ,  Il-Man Bae ,  Jong-Hyun Choi

IPC分类号： G11C7/10 ,  G11C5/14

CPC分类号： G11C11/4085 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/065 ,  G11C2207/2227

摘要： In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.

公开(公告)号：US06930948B2

公开(公告)日：2005-08-16

申请号：US10621165

申请日：2003-07-15

申请人： Kyu-Chan Lee ,  Sang-Jae Rhee ,  Jung-Yong Choi ,  Jong-Hyun Choi ,  Jong-Sik Na ,  Jae-Hoon Kim

发明人： Kyu-Chan Lee ,  Sang-Jae Rhee ,  Jung-Yong Choi ,  Jong-Hyun Choi ,  Jong-Sik Na ,  Jae-Hoon Kim

IPC分类号： G11C5/14 ,  G11C11/00

CPC分类号： G11C5/147

摘要： An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

摘要翻译： 外部高/低电压兼容半导体存储器件包括内部电压焊盘，内部电压产生电路和内部电压控制信号产生电路。 内部电压焊盘将低外部电压与内部电压连接，并且内部电压产生电路响应于内部电压控制信号和高外部电压而产生内部电压。 内部电压控制信号发生电路根据高或低的外部电压产生内部电压控制信号。 因此，由于内部电压控制信号，可以管理半导体存储器件的数据库，而不将数据库分类为用于低电压的高电压数据库和数据库。 此外，内部电压电平稳定，因为根据外部电压的电压电平调节提供给内部电压的电荷。

公开(公告)号：US6026038A

公开(公告)日：2000-02-15

申请号：US935613

申请日：1997-09-23

申请人： Soo-In Cho ,  Jong-Hyun Choi

发明人： Soo-In Cho ,  Jong-Hyun Choi

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C7/00 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C29/025 ,  G11C29/006 ,  G11C29/02 ,  G11C29/50 ,  G11C11/401

摘要： A wafer burn-in test circuit of a semiconductor memory device having a plurality of memory cells arranged in a row/column matrix, is provided, including: a sub word line driver connected to first and second word line groups each connected to true cells and complement cells forming the memory cells, and responding to a predecoded low address; and first and second power lines respectively supplying power to the corresponding first and second power line groups by a switching operation of the sub word line driver, wherein a ground power source is applied to the first and second power lines during a normal operation, and the ground power source and a step-up power source are alternately applied to the first and second power lines during a wafer burn-in test operation.

摘要翻译： 提供了具有以行/列矩阵排列的多个存储单元的半导体存储器件的晶片老化测试电路，包括：连接到每个连接到真实单元的第一和第二字线组的子字线驱动器，以及 形成存储器单元的补码单元，以及对预解码的低地址的响应; 以及分别通过子字线驱动器的切换操作向对应的第一和第二电力线组提供电力的第一和第二电力线，其中在正常操作期间将地电源施加到第一和第二电力线，并且 接地电源和升压电源在晶片老化测试操作期间交替施加到第一和第二电源线。

公开(公告)号：US5267203A

公开(公告)日：1993-11-30

申请号：US792588

申请日：1991-11-15

申请人： Hong-Seon Hwang ,  Jong-Hyun Choi

发明人： Hong-Seon Hwang ,  Jong-Hyun Choi

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/065

摘要： A sense amplifier control circuit for controlling the voltage applied to a sense amplifier and a memory cell by setting the voltage as a given level (in this case, 4 V) is provided. The sense amplifier control circuit being inputted by the voltage applied to the sense amplifier and the memory cell thereto and generating the output voltage to the gate of the sense amplifier driver includes a comparator for operating whenever the voltage applied to the sense amplifier and memory cell is varied, a level shift circuit for converting an internal power voltage into an external power voltage, a trigger circuit, a driver control circuit and a bias circuit for constantly maintaining the current flowing into the driving element of the driver control circuit. Therefore, the voltage applied to the sense amplifier and memory cell come to have an appropriate rising slope, and after reached to the given level, the control circuit controls the level to be continuously maintained. Consequently, the wrong operation of a chip and the power noise is reduced, to thus improve the reliability of a semiconductor memory device.

摘要翻译： 提供了一种用于通过将电压设置为给定电平（在这种情况下为4V）来控制施加到读出放大器和存储单元的电压的读出放大器控制电路。 读出放大器控制电路由施加到感测放大器和存储单元的电压输入，并产生到读出放大器驱动器的栅极的输出电压包括一个比较器，用于每当施加到感测放大器和存储单元的电压为 用于将内部电源电压转换为外部电源电压的电平移位电路，触发电路，驱动器控制电路和偏置电路，用于不断地保持流入驱动器控制电路的驱动元件的电流。 因此，施加到感测放大器和存储单元的电压具有适当的上升斜率，并且在达到给定电平之后，控制电路控制电平被连续保持。 因此，芯片的错误操作和功率噪声被降低，从而提高了半导体存储器件的可靠性。

公开(公告)号：US09818707B2

公开(公告)日：2017-11-14

申请号：US14960909

申请日：2015-12-07

申请人： Ki-Seok Oh ,  Doo-Hee Hwang ,  Dong-Yang Lee ,  Jong-Hyun Choi

发明人： Ki-Seok Oh ,  Doo-Hee Hwang ,  Dong-Yang Lee ,  Jong-Hyun Choi

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L25/065 ,  H01L27/18 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  G11C7/10

CPC分类号： H01L24/06 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/105 ,  H01L25/0657 ,  H01L27/18 ,  H01L27/222 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L2224/09515 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/1434

摘要： A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a chip command-address pad unit, a lower chip data pad unit and an upper chip data pad unit that are to be connected to an external device. The first semiconductor die electrically is connected to the chip command-address pad unit and the lower chip data pad unit and electrically disconnected from the upper chip data pad unit. The second semiconductor die electrically is connected to the chip command-address pad unit and the upper chip data pad unit and electrically disconnected from the lower chip data pad unit. The input-output load may be reduced by selectively connecting each of the stacked semiconductor dies to one of the lower chip data pad unit and the upper chip data pad unit.

公开(公告)号：US09368751B2

公开(公告)日：2016-06-14

申请号：US13416108

申请日：2012-03-09

申请人： Seong-Kweon Heo ,  Ki-Nyeng Kang ,  Jong-Hyun Choi

发明人： Seong-Kweon Heo ,  Ki-Nyeng Kang ,  Jong-Hyun Choi

IPC分类号： H01L51/52 ,  H01L27/12 ,  H01L29/49 ,  H01L27/32

CPC分类号： H01L51/5259 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L29/4908 ,  H01L51/5246

摘要： An organic light-emitting display apparatus includes a thin film transistor on a display region of a substrate, the thin film transistor facing an encapsulation member, an organic light-emitting device on the display region that includes an intermediate layer having an organic emission layer, a sealing member that is between the substrate and the encapsulation member and that surrounds the display region, an internal circuit unit between the display region and the sealing member, a passivation layer that extends to cover the internal circuit unit, a pixel defining layer on the passivation layer, and a getter between the substrate and the encapsulation member, and the getter at least partially overlapping the internal circuit unit.

摘要翻译： 一种有机发光显示装置，包括在基板的显示区域上的薄膜晶体管，薄膜晶体管面向封装构件，在显示区域上的有机发光器件，其包括具有有机发射层的中间层， 密封构件，位于衬底和封装构件之间，并且围绕显示区域，在显示区域和密封构件之间的内部电路单元，延伸以覆盖内部电路单元的钝化层，位于显示区域和密封构件之间的像素限定层 钝化层和衬底和封装构件之间的吸气剂，并且吸气剂至少部分地与内部电路单元重叠。