公开(公告)号：US20090170254A1

公开(公告)日：2009-07-02

申请号：US12343134

申请日：2008-12-23

申请人： Hwa-Sung Rhee ,  Ho Lee ,  Myung-Sun Kim ,  Ji-Hye Yi

发明人： Hwa-Sung Rhee ,  Ho Lee ,  Myung-Sun Kim ,  Ji-Hye Yi

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.

摘要翻译： 在制造半导体器件的方法中，第一栅电极和第二栅电极形成在衬底的第一区域和第二区域中。 在与第一栅电极相邻的衬底的第一区域中形成非结晶区域。 在基板和第一和第二栅电极上形成具有第一应力的层。 掩模在衬底的第一区域中的该层的第一部分上形成以暴露第二区域中该层的第二部分。 蚀刻第二部分以在第二栅电极的侧壁上形成牺牲间隔物。 使用掩模，第二栅电极和牺牲隔离物部分蚀刻衬底的第二区域，以在与第二栅电极相邻的衬底的第二区域中形成凹陷。 在凹部中形成具有第二应力的图案。

公开(公告)号：US20080272366A1

公开(公告)日：2008-11-06

申请号：US12010806

申请日：2008-01-30

申请人： Chang-wook Moon ,  Joong S. Jeon ,  Jung-hyun Lee ,  Nae-in Lee ,  Yeon-sik Park ,  Hwa-sung Rhee ,  Ho Lee ,  Se-young Cho ,  Suk-pil Kim

发明人： Chang-wook Moon ,  Joong S. Jeon ,  Jung-hyun Lee ,  Nae-in Lee ,  Yeon-sik Park ,  Hwa-sung Rhee ,  Ho Lee ,  Se-young Cho ,  Suk-pil Kim

IPC分类号： H01L29/12 ,  H01L21/336

CPC分类号： H01L29/66439 ,  B82Y10/00 ,  B82Y15/00 ,  H01L21/02356 ,  H01L21/02365 ,  H01L21/02601 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/66742 ,  H01L29/7839 ,  H01L29/78684 ,  H01L29/78696 ,  H01L51/426 ,  H01L2221/1094

摘要： A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate oxide layer formed on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate oxide layer between the source electrode and the drain electrode.

摘要翻译： 提供具有至少一个Ge纳米棒的场效应晶体管和制造场效应晶体管的方法。 场效应晶体管可以包括形成在硅衬底上的栅氧化层，至少一个纳米棒嵌入在其两端被暴露的栅极氧化层中，源电极和漏极连接到至少一个Ge纳米棒的相对侧 以及形成在源电极和漏电极之间的栅氧化层上的栅电极。

公开(公告)号：US07879668B2

公开(公告)日：2011-02-01

申请号：US12343134

申请日：2008-12-23

申请人： Hwa-Sung Rhee ,  Ho Lee ,  Myung-Sun Kim ,  Ji-Hye Yi

发明人： Hwa-Sung Rhee ,  Ho Lee ,  Myung-Sun Kim ,  Ji-Hye Yi

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.

摘要翻译： 在制造半导体器件的方法中，第一栅电极和第二栅电极形成在衬底的第一区域和第二区域中。 在与第一栅电极相邻的衬底的第一区域中形成非结晶区域。 在基板和第一和第二栅电极上形成具有第一应力的层。 掩模在衬底的第一区域中的该层的第一部分上形成以暴露第二区域中该层的第二部分。 蚀刻第二部分以在第二栅电极的侧壁上形成牺牲间隔物。 使用掩模，第二栅电极和牺牲隔离物部分蚀刻衬底的第二区域，以在与第二栅电极相邻的衬底的第二区域中形成凹陷。 在凹部中形成具有第二应力的图案。

公开(公告)号：US20100233864A1

公开(公告)日：2010-09-16

申请号：US12656842

申请日：2010-02-17

申请人： Ho Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Myung-sun Kim ,  Hoi-sung Chung

发明人： Ho Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Myung-sun Kim ,  Hoi-sung Chung

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/76825 ,  H01L21/76829 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： Methods of fabricating a semiconductor device are provided, the methods include forming a gate stack on a substrate, forming an insulation layer on the substrate to cover the gate stack, forming a spacer at both side walls of the gate stack by etching the insulation layer, and ion implanting impurities in the spacer or the insulation layer.

摘要翻译： 提供了制造半导体器件的方法，所述方法包括在衬底上形成栅极堆叠，在衬底上形成绝缘层以覆盖栅极堆叠，通过蚀刻绝缘层在栅极堆叠的两个侧壁处形成间隔物， 以及在间隔物或绝缘层中离子注入杂质。

公开(公告)号：US08741710B2

公开(公告)日：2014-06-03

申请号：US12248431

申请日：2008-10-09

申请人： Dong-Suk Shin ,  Ho Lee ,  Tae-Gyun Kim

发明人： Dong-Suk Shin ,  Ho Lee ,  Tae-Gyun Kim

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/8238 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/8234 ,  H01L21/823475 ,  H01L21/823871 ,  H01L29/665

摘要： Semiconductor devices are fabricated using a plasma process with a non-silane gas that includes deuterium, and which may result in improved device reliability and/or other improved device operational characteristics. One such method can include forming a gate oxide layer on a transistor region, which is defined on a substrate, and forming a gate electrode on the gate oxide layer. An etch stop layer is formed on the gate oxide layer and the gate electrode. A plasma process is performed on the interface between the gate oxide layer and the substrate using a non-silane treatment gas including deuterium. An interlayer dielectric layer is formed on the etch stop layer. A bottom metal line is formed on the interlayer dielectric layer.

摘要翻译： 使用包括氘的非硅烷气体的等离子体工艺制造半导体器件，并且其可以导致改进的器件可靠性和/或其他改进的器件操作特性。 一种这样的方法可以包括在限定在衬底上的晶体管区域上形成栅极氧化层，并在栅极氧化物层上形成栅电极。 在栅极氧化物层和栅电极上形成蚀刻停止层。 使用包括氘的非硅烷处理气体在栅极氧化物层和衬底之间的界面上进行等离子体处理。 在蚀刻停止层上形成层间电介质层。 底层金属线形成在层间电介质层上。

公开(公告)号：US20090224287A1

公开(公告)日：2009-09-10

申请号：US12400408

申请日：2009-03-09

申请人： Dong-Suk Shin ,  Ho Lee ,  Myung-Sun Kim

发明人： Dong-Suk Shin ,  Ho Lee ,  Myung-Sun Kim

IPC分类号： H01L29/80

CPC分类号： H01L29/1083 ,  H01L21/76267 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device having a locally buried insulation layer and a method of manufacturing a semiconductor device having the same are provided, in which a gate electrode is formed on a substrate, and oxygen ions are implanted into an active region to form a locally buried insulation layer. An impurity layer is formed on the locally buried insulation layer to form a source/drain. A silicide layer is formed on the source/drain and on the gate electrode. The locally buried insulation layer can prevent junction leakage, decrease junction capacitance and prevent a critical voltage of an MOS transistor from increasing due to body bias, thereby to improve characteristics of the device.

摘要翻译： 提供了具有局部掩埋绝缘层的半导体器件及其制造方法，其中在基板上形成栅电极，并将氧离子注入有源区以形成局部掩埋的绝缘层 。 在局部掩埋的绝缘层上形成杂质层以形成源极/漏极。 在源极/漏极和栅电极上形成硅化物层。 局部埋入绝缘层可以防止结漏电，降低结电容，并防止MOS晶体管的临界电压由于体偏压而增加，从而改善器件的特性。

公开(公告)号：US20090104741A1

公开(公告)日：2009-04-23

申请号：US12248431

申请日：2008-10-09

申请人： Dong-Suk Shin ,  Ho Lee ,  Tae-Gyun Kim

发明人： Dong-Suk Shin ,  Ho Lee ,  Tae-Gyun Kim

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/8238 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/8234 ,  H01L21/823475 ,  H01L21/823871 ,  H01L29/665

摘要： Semiconductor devices are fabricated using a plasma process with a non-silane gas that includes deuterium, and which may result in improved device reliability and/or other improved device operational characteristics. One such method can include forming a gate oxide layer on a transistor region, which is defined on a substrate, and forming a gate electrode on the gate oxide layer. An etch stop layer is formed on the gate oxide layer and the gate electrode. A plasma process is performed on the interface between the gate oxide layer and the substrate using a non-silane treatment gas including deuterium. An interlayer dielectric layer is formed on the etch stop layer. A bottom metal line is formed on the interlayer dielectric layer.

摘要翻译： 使用包括氘的非硅烷气体的等离子体工艺制造半导体器件，并且其可以导致改进的器件可靠性和/或其他改进的器件操作特性。 一种这样的方法可以包括在限定在衬底上的晶体管区域上形成栅极氧化层，并在栅极氧化物层上形成栅电极。 在栅极氧化物层和栅电极上形成蚀刻停止层。 使用包括氘的非硅烷处理气体在栅极氧化物层和衬底之间的界面上进行等离子体处理。 在蚀刻停止层上形成层间电介质层。 底层金属线形成在层间电介质层上。

公开(公告)号：US20110136311A1

公开(公告)日：2011-06-09

申请号：US13028654

申请日：2011-02-16

申请人： Dong-Suk SHIN ,  Ho Lee ,  Myung-Sun Kim

发明人： Dong-Suk SHIN ,  Ho Lee ,  Myung-Sun Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/1083 ,  H01L21/76267 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device having a locally buried insulation layer and a method of manufacturing a semiconductor device having the same are provided, in which a gate electrode is formed on a substrate, and oxygen ions are implanted into an active region to form a locally buried insulation layer. An impurity layer is formed on the locally buried insulation layer to form a source/drain. A silicide layer is formed on the source/drain and on the gate electrode. The locally buried insulation layer can prevent junction leakage, decrease junction capacitance and prevent a critical voltage of an MOS transistor from increasing due to body bias, thereby to improve characteristics of the device.

摘要翻译： 提供了具有局部掩埋绝缘层的半导体器件及其制造方法，其中在基板上形成栅电极，并将氧离子注入有源区以形成局部掩埋的绝缘层 。 在局部掩埋的绝缘层上形成杂质层以形成源极/漏极。 在源极/漏极和栅电极上形成硅化物层。 局部埋入绝缘层可以防止结漏电，降低结电容，并防止MOS晶体管的临界电压由于体偏压而增加，从而改善器件的特性。

公开(公告)号：US07682888B2

公开(公告)日：2010-03-23

申请号：US11435968

申请日：2006-05-17

申请人： Ho Lee ,  Tetsuji Ueno ,  Hwa-Sung Rhe

发明人： Ho Lee ,  Tetsuji Ueno ,  Hwa-Sung Rhe

IPC分类号： H01L21/4763

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02293 ,  H01L21/3147 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.

摘要翻译： 形成集成电路的方法包括：在与其100°晶体取向平行的衬底上选择性地形成用于NMOS和PMOS晶体管的有源沟道区，并且选择性地形成具有碳（C）杂质的NMOS晶体管的源极/漏极区。

公开(公告)号：US20070048907A1

公开(公告)日：2007-03-01

申请号：US11435968

申请日：2006-05-17

申请人： Ho Lee ,  Tetsuji Ueno ,  Hwa-Sung Rhe

发明人： Ho Lee ,  Tetsuji Ueno ,  Hwa-Sung Rhe

IPC分类号： H01L21/8232 ,  H01L21/335

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02293 ,  H01L21/3147 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.

摘要翻译： 形成集成电路的方法包括：在与其100°晶体取向平行的衬底上选择性地形成用于NMOS和PMOS晶体管的有源沟道区，并且选择性地形成具有碳（C）杂质的NMOS晶体管的源极/漏极区。