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    METAL GATE FOR A FIELD EFFECT TRANSISTOR AND METHOD
    61.
    发明申请
    METAL GATE FOR A FIELD EFFECT TRANSISTOR AND METHOD 审中-公开

    公开(公告)号：US20200335602A1

    公开(公告)日：2020-10-22

    申请号：US16390473

    申请日：2019-04-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Tao Chu ,  Rongtao Lu ,  Ayse M. Ozbek ,  Wei Ma ,  Haiting Wang

    IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

    Abstract: Disclosed is a metal gate (e.g., a replacement metal gate (RMG) for a field effect transistor (FET) and a method of forming the metal gate. The method includes depositing a conformal dielectric layer to line a gate opening and performing a series of unclustered and clustered conformal metal deposition and chamfer processes to selectively adjust the heights of conformal metal layers within the gate opening. By selectively controlling the heights of the conformal metal layers, the method provides improved overall gate height control and gate quality particularly when the metal gate has a small critical dimension (CD) and/or a high aspect ratio (AR). The method can also include using different etch techniques during the different chamfer processes and, particularly, when different materials and/or different material interfaces are exposed to an etchant in order to ensure an essentially uniform etch rate of the conformal metal layer(s) at issue in a direction that is essentially vertical.

    Method of forming gate structure with undercut region and resulting device
    63.
    发明授权
    Method of forming gate structure with undercut region and resulting device 有权

    公开(公告)号：US10727133B2

    公开(公告)日：2020-07-28

    申请号：US16134708

    申请日：2018-09-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Qun Gao ,  Balaji Kannan ,  Shesh Mani Pandey ,  Haiting Wang

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

    Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.

    METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR FINFET DEVICES WITH REDUCED PARASITIC CAPACITANCE
    65.
    发明申请
    METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR FINFET DEVICES WITH REDUCED PARASITIC CAPACITANCE 审中-公开

    公开(公告)号：US20200105905A1

    公开(公告)日：2020-04-02

    申请号：US16144275

    申请日：2018-09-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui Zang ,  Haiting Wang ,  Ruilong Xie

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78

    Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced parasitic capacitance between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including first and second fins; an isolation structure between the fins; first and second metal gates; a first dielectric body under the first metal gate and on the substrate between the first fin and the second fin, wherein a top of the first dielectric body is below a top of the first metal gate; and a second dielectric body in the second metal gate and on the substrate between the first fin and the second fin, wherein a top of the second dielectric body is at or above a top of the second metal gate.

    Integrated single diffusion break
    67.
    发明授权
    Integrated single diffusion break 有权

    公开(公告)号：US10580685B2

    公开(公告)日：2020-03-03

    申请号：US16047078

    申请日：2018-07-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui Zang ,  Haiting Wang ,  Hong Yu ,  Laertis Economikos

    IPC: H01L23/522 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/764

    Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.

    USING SOURCE/DRAIN CONTACT CAP DURING GATE CUT
    68.
    发明申请
    USING SOURCE/DRAIN CONTACT CAP DURING GATE CUT 审中-公开

    公开(公告)号：US20200020687A1

    公开(公告)日：2020-01-16

    申请号：US16032108

    申请日：2018-07-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Haiting Wang ,  Shesh Mani Pandey ,  Jiehui Shu ,  Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Guowei Xu ,  Zhaoying Hu

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

    Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.

    Different upper and lower spacers for contact
    69.
    发明授权
    Different upper and lower spacers for contact 有权

    公开(公告)号：US10522644B1

    公开(公告)日：2019-12-31

    申请号：US16014076

    申请日：2018-06-21

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Scott Beasor

    IPC: H01L27/088 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

    Abstract: Various processes form different structures including exemplary apparatuses that include (among other components) a first layer having channel regions, source/drain structures in the first layer on opposite sides of the channel regions, a gate insulator on the channel region, and a gate stack on the gate insulator. The gate stack can include a gate conductor, and a stack insulator or a gate contact on the gate conductor. The gate stack has lower sidewalls adjacent to the source/drain structures and upper sidewalls distal to the source/drain structures. Further, lower spacers are between the source/drain contacts and the lower sidewalls of the gate stack; and upper spacers between the source/drain contacts and the upper sidewalls of the gate stack. In some structures, the upper spacers can partially overlap the lower spacers.

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