公开(公告)号：US09722057B2

公开(公告)日：2017-08-01

申请号：US14747668

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Marwan H. Khater

IPC: H01L29/737 ,  H01L21/265 ,  H01L21/762 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L21/26586 ,  H01L21/76237 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732

Abstract: Device structure and fabrication methods for a bipolar junction transistor. A trench isolation region is formed that bounds an active device region along a sidewall. A dielectric region is formed that extends laterally from the sidewall of the active device region into the active device region. The dielectric region is located beneath a top surface of the active device region such that a section of the active device region is located between the top surface and the dielectric region.

公开(公告)号：US20160372582A1

公开(公告)日：2016-12-22

申请号：US14745704

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Hanyi Ding ,  Natalie B. Feilchenfeld ,  Vibhor Jain ,  Anthony K. Stamper

IPC: H01L29/73 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/732

CPC classification number: H01L29/0821 ,  H01L21/762 ,  H01L21/76283 ,  H01L29/0653 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7371

Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

Abstract translation: 使用包括高电阻处理晶片的绝缘体上硅衬底形成器件结构和器件结构的方法。 在高电阻处理晶片中形成掺杂区域。 形成第一沟槽，其延伸穿过绝缘体上硅衬底的器件层和掩埋绝缘体层到高电阻处理晶片。 掺杂区域包括在第一沟槽横向延伸的掺杂区域的横向延伸。 半导体层在第一沟槽内外延生长，并且使用半导体层的至少一部分形成器件结构。 形成第二沟槽，其延伸穿过器件层和掩埋绝缘体层到掺杂区域的横向延伸，并且在第二沟槽中形成导电插塞。 掺杂区域和插塞包括身体接触。

公开(公告)号：US10923577B2

公开(公告)日：2021-02-16

申请号：US16241441

申请日：2019-01-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Johnatan A. Kantarovsky ,  Siva P. Adusumilli ,  Vibhor Jain

IPC: H01L29/00 ,  H01L29/51 ,  H01L21/762 ,  H01L49/02 ,  H01L29/161 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/764

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. The structure includes: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.

公开(公告)号：US10916642B2

公开(公告)日：2021-02-09

申请号：US16388500

申请日：2019-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

公开(公告)号：US20200235729A1

公开(公告)日：2020-07-23

申请号：US16252007

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain

IPC: H03K17/14 ,  G05D23/19 ,  G05D23/24 ,  H01C7/04 ,  G01K3/00

Abstract: One illustrative device includes, among other things, an active device comprising a first terminal, a first bias resistor connected to the first terminal, and a first resistor comprising a first phase transition material connected in parallel with the first bias transistor, wherein the first phase transition material exhibits a first low conductivity phase for temperatures less than a first phase transition temperature and a first high conductivity phase for temperatures greater than the first phase transition temperature.

公开(公告)号：US20190326411A1

公开(公告)日：2019-10-24

申请号：US15961364

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Pernell Dongmo ,  Cameron Luce ,  James W. Adkisson ,  Qizhi Liu

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.

公开(公告)号：US10439053B2

公开(公告)日：2019-10-08

申请号：US16394421

申请日：2019-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L27/12 ,  H01L23/535 ,  H01L21/768 ,  H01L21/02 ,  H01L21/84

Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

公开(公告)号：US20190267304A1

公开(公告)日：2019-08-29

申请号：US16405325

申请日：2019-05-07

Applicant: GlobalFoundries Inc.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L23/367 ,  H01L29/732 ,  H01L29/66 ,  H01L29/08 ,  H01L21/48 ,  H01L29/417

Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

公开(公告)号：US10367084B2

公开(公告)日：2019-07-30

申请号：US15664418

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L27/12 ,  H01L23/535 ,  H01L21/02 ,  H01L21/768 ,  H01L21/84 ,  H01L29/165

Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

公开(公告)号：US10367083B2

公开(公告)日：2019-07-30

申请号：US15081443

申请日：2016-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L21/762 ,  H01L29/73

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.