-
公开(公告)号：US20100010784A1
公开(公告)日：2010-01-14
申请号：US12475080
申请日：2009-05-29
IPC分类号： G06F17/50
CPC分类号： B29C67/0088 , B29C64/386 , G03F7/70091 , G03F7/70458 , G03F7/705 , G03F7/70516 , G03F7/70525 , G06F17/50 , G06F17/5009 , G06F17/5081
摘要： Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.
摘要翻译： 描述用于调整光刻工艺的系统和方法。 保持目标扫描仪的型号，参考一组可调谐参数来定义目标扫描仪的灵敏度。 差分模型表示目标扫描器与参考值的偏差。 可以基于参考扫描仪和差分模型的设置来调整目标扫描仪。 可以相对于参考扫描仪的性能来表征相关扫描仪系列的性能。 差分模型可能包括诸如参数偏移和可能用于模拟成像行为差异的其他差异的信息。
-
公开(公告)号：US20090276751A1
公开(公告)日：2009-11-05
申请号：US12417559
申请日：2009-04-02
申请人： Yu Cao , James Norman Wiley , Jun Ye
发明人： Yu Cao , James Norman Wiley , Jun Ye
IPC分类号： G06F17/50
摘要： A model-based tuning method for tuning a first mask writer unit utilizing a reference mask writer unit, each of which has tunable parameters for controlling mask writing performance. The method includes the steps of defining a test pattern and a mask writing model; generating the test pattern utilizing the reference mask writer unit and measuring the mask writing results; generating the test pattern utilizing the first mask writer unit and measuring the mask writing results; calibrating the mask writing model utilizing the mask writing results corresponding to the reference mask writer unit, where the calibrated mask writing model has a first set of parameter values; tuning the calibrated mask writing model utilizing the mask writing results corresponding to the first mask writer unit, where the tuned calibrated model has a second set of parameter values; and adjusting the parameters of the first mask writer unit based on a difference between the first set of parameter values and the second set of parameter values.
摘要翻译： 一种基于模型的调谐方法，用于利用参考掩模写入器单元调整第一掩模写入器单元，每个参考掩码写入器单元具有用于控制掩模写入性能的可调参数。 该方法包括定义测试图案和掩模书写模型的步骤; 使用参考掩模写入器单元产生测试图案并测量掩模写入结果; 使用第一掩模写入器单元产生测试图案并测量掩模写入结果; 使用对应于参考掩模写入器单元的掩模写入结果来校准掩模写入模型，其中校准的掩模写入模型具有第一组参数值; 使用对应于第一掩模写入器单元的掩模写入结果调整校准的掩模写入模型，其中调谐的校准模型具有第二组参数值; 以及基于所述第一组参数值和所述第二组参数值之间的差来调整所述第一掩模写入器单元的参数。
-
63.发明申请SYSTEM AND METHOD FOR CREATING A FOCUS-EXPOSURE MODEL OF A LITHOGRAPHY PROCESS 有权用于创建光刻过程的聚焦曝光模型的系统和方法公开(公告)号：US20070031745A1
公开(公告)日：2007-02-08
申请号：US11461994
申请日：2006-08-02
申请人： Jun Ye , Yu Cao , Luoqi Chen , Hua-Yu Liu
发明人： Jun Ye , Yu Cao , Luoqi Chen , Hua-Yu Liu
CPC分类号： G03F7/70641 , G03F7/705 , G03F7/70516 , G03F7/70625
摘要： A system and a method for creating a focus-exposure model of a lithography process are disclosed. The system and the method utilize calibration data along multiple dimensions of parameter variations, in particular within an exposure-defocus process window space. The system and the method provide a unified set of model parameter values that result in better accuracy and robustness of simulations at nominal process conditions, as well as the ability to predict lithographic performance at any point continuously throughout a complete process window area without a need for recalibration at different settings. With a smaller number of measurements required than the prior-art multiple-model calibration, the focus-exposure model provides more predictive and more robust model parameter values that can be used at any location in the process window.
摘要翻译： 公开了一种用于创建光刻工艺的聚焦曝光模型的系统和方法。 系统和方法利用参数变化的多个维度的校准数据，特别是在曝光 - 散焦过程窗口空间内。 该系统和方法提供了一套统一的模型参数值，可在标称工艺条件下提供更好的模拟精度和鲁棒性，以及能够在整个过程窗口区域内连续预测任何点的光刻性能，而无需 重新校准在不同的设置。 与现有技术的多模型校准相比，要进行的测量数量要少一些，聚焦曝光模型提供了更多的预测性和更健壮的模型参数值，可以在过程窗口中的任何位置使用。
-
公开(公告)号：US07111277B2
公开(公告)日：2006-09-19
申请号：US10981914
申请日：2004-11-04
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
-
65.发明授权公开(公告)号：US06516085B1
公开(公告)日：2003-02-04
申请号：US09304437
申请日：1999-05-03
申请人： James N. Wiley , Jun Ye , Shauh-Teh Juang , David S. Alles , Yen-Wen Lu , Yu Cao
发明人： James N. Wiley , Jun Ye , Shauh-Teh Juang , David S. Alles , Yen-Wen Lu , Yu Cao
IPC分类号： G06K900
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of inspecting a reticle defining a circuit layer pattern that is used within a corresponding semiconductor process to generate corresponding patterns on a semiconductor wafer. A test image of the reticle is provided, and the test image has a plurality of test characteristic values. A baseline image containing an expected pattern of the test image is also provided. The baseline image has a plurality of baseline characteristic values that correspond to the test characteristic values. The test characteristic values are compared to the baseline characteristic values such that a plurality of difference values are calculated for each pair of test and baseline characteristic values. Statistical information is also collected.
摘要翻译： 公开了一种检查限定在相应半导体工艺中使用的电路层图案的掩模版的方法，以在半导体晶片上产生相应的图案。 提供了掩模版的测试图像，并且测试图像具有多个测试特性值。 还提供了包含测试图像的预期图案的基线图像。 基线图像具有对应于测试特征值的多个基线特征值。 将测试特征值与基线特征值进行比较，使得针对每对测试和基线特征值计算多个差值。 还收集统计资料。
-
公开(公告)号：US06414788B1
公开(公告)日：2002-07-02
申请号：US09711923
申请日：2000-11-15
申请人： Jun Ye , Yen-Wen Lu , Yu Cao
发明人： Jun Ye , Yen-Wen Lu , Yu Cao
IPC分类号： H04B1012
CPC分类号： H04B10/296 , H01S3/06754 , H01S3/10015 , H01S3/1301 , H01S2301/04
摘要： Optical amplifiers are provided that use a hybrid transient control scheme. Optical taps may be used to tap the main fiber path through the amplifier before and after the gain stage. The gain stage may be provided by one or more rare-earth-doped fiber coils such as erbium-doped fiber coils. The coils may be pumped by laser diodes or other suitable pumps. The optical output power of the pumps may be controlled by a controller. The controller may calculate the appropriate power to be applied by the pumps based on the measured input and output signal powers of the amplifier. The control process implemented by the controller may be based on a combination of feedback and feed-forward control techniques.
摘要翻译： 提供了使用混合瞬态控制方案的光放大器。 光学抽头可以用于在增益级之前和之后通过放大器分接主光纤路径。 增益级可以由一个或多个稀土掺杂光纤线圈提供，例如掺铒光纤线圈。 线圈可以由激光二极管或其它合适的泵泵送。 泵的光输出功率可由控制器控制。 控制器可以基于所测量的放大器的输入和输出信号功率来计算由泵施加的适当功率。 由控制器实现的控制过程可以基于反馈和前馈控制技术的组合。
-
公开(公告)号：US09645509B2
公开(公告)日：2017-05-09
申请号：US12608460
申请日：2009-10-29
申请人： Yu Cao , Jun Ye , James Patrick Koonmen , Stefan Hunsche
发明人： Yu Cao , Jun Ye , James Patrick Koonmen , Stefan Hunsche
CPC分类号： G03F7/705 , G03F7/70508 , G03F7/70666
摘要： The present invention relates to a method for simulating aspects of a lithographic process. According to certain aspects, the present invention uses transmission cross coefficients to represent the scanner data and models. According to other aspects, the present invention enables sensitive data regarding various scanner subsystems to be hidden from third party view, while providing data and models useful for accurate lithographic simulation.
-
公开(公告)号：US09459537B2
公开(公告)日：2016-10-04
申请号：US13530065
申请日：2012-06-21
CPC分类号： G03F7/70133 , G03F7/705 , G03F7/70525 , G03F7/70616
摘要： The present invention discloses various system and process embodiments where wafer-metrology and direct measurements of the lithography apparatus characteristics are combined to achieve temporal drift reduction in a lithography apparatus/process using a simulation model. The simulation model may have sub-components. For example, a sub-model may represent a first set of optical conditions, and another sub-model may represent a second set of optical conditions. The first set of optical conditions may be a standard set of illumination conditions, and the second set may be a custom set of illumination conditions. Using the inter-relationship of the sub-models, stability control under custom illumination condition can be achieved faster without wafer metrology.
摘要翻译： 本发明公开了各种系统和工艺实施例，其中组合光刻设备特性的晶片计量和直接测量以在使用仿真模型的光刻设备/工艺中实现时间漂移减小。 仿真模型可能具有子组件。 例如，子模型可以表示第一组光学条件，而另一个子模型可以表示第二组光学条件。 第一组光学条件可以是标准的照明条件集合，并且第二组可以是定制的照明条件集合。 使用子模型的相互关系，在没有晶片计量的情况下，可以更快地实现定制照明条件下的稳定性控制。
-
公开(公告)号：US20120269421A1
公开(公告)日：2012-10-25
申请号：US13533942
申请日：2012-06-26
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luogi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luogi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.
摘要翻译： 在一个方面，本发明涉及用于模拟，验证，检查，表征，确定和/或评估光刻设计，技术和/或系统的技术和系统，和/或由其执行的各个功能或使用的组件 其中。 在一个实施例中，本发明是加速光刻特性和/或性质的光刻模拟，检查，表征和/或评估以及光刻系统和处理技术的效果和/或相互作用的系统和方法。
-
公开(公告)号：US20110083113A1
公开(公告)日：2011-04-07
申请号：US12964697
申请日：2010-12-09
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
摘要翻译： 这里描述和说明了许多发明。 在一个方面，本发明涉及用于模拟，验证，检查，表征，确定和/或评估光刻设计，技术和/或系统的技术和系统，和/或由其执行的单独功能或所使用的组件 其中。 在一个实施例中，本发明是加速光刻特性和/或性质的光刻模拟，检查，表征和/或评估以及光刻系统和处理技术的效果和/或相互作用的系统和方法。 在这方面，在一个实施例中，本发明采用光刻仿真系统架构，包括特定于应用的硬件加速器，以及用于加速和促进掩模设计的验证，表征和/或检验的处理技术，例如RET设计 ，包括对整个光刻工艺进行详细的仿真和表征，以验证设计在最终的晶片图案上实现和/或提供期望的结果。 该系统包括：（1）通用目的型计算设备，用于执行在数据处理中具有分支和相互依赖性的基于案例的逻辑，以及（2）加速器子系统执行大部分计算密集型任务。
-
-
-
-
-
-
-
-
-
搜索结果
241 条记录 (耗时 0.041 秒)
