公开(公告)号：US06723572B2

公开(公告)日：2004-04-20

申请号：US10139278

申请日：2002-05-07

申请人： Hiroyuki Yano ,  Katsuya Okumura

发明人： Hiroyuki Yano ,  Katsuya Okumura

IPC分类号： H01L2166

CPC分类号： H01L22/26 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A to-be-polished surface of a semiconductor workpiece is polished to a target shape, using a CMP tool. The to-be-polished surface is a surface of a metal provided on an insulating film having trenches. A shape of a polished surface of the semiconductor workpiece is monitored to determine if a metal residue exists outside of the trenches on the polished surface while the semiconductor workpiece is set in the CMP tool, using a monitor. The monitor has a sensor that obtains a two-dimensional image of the to-be-polished surface. The CMP tool is controlled by feedback based on a result of monitoring to determine if the metal residue exists, using a controller.

摘要翻译： 使用CMP工具将半导体工件的待抛光表面抛光至目标形状。 被抛光表面是设置在具有沟槽的绝缘膜上的金属表面。 监测半导体工件的抛光表面的形状，以确定当使用监视器将半导体工件设置在CMP工具中时，金属残留物是否存在于抛光表面上的沟槽外部。 显示器具有获得被抛光表面的二维图像的传感器。 CMP工具由基于监测结果的反馈控制，以使用控制器确定是否存在金属残留物。

公开(公告)号：US06633045B1

公开(公告)日：2003-10-14

申请号：US09667521

申请日：2000-09-22

申请人： Kazuyoshi Sugihara ,  Atsushi Ando ,  Katsuya Okumura

发明人： Kazuyoshi Sugihara ,  Atsushi Ando ,  Katsuya Okumura

IPC分类号： G21G500

CPC分类号： H05K3/0061 ,  H01J2237/3175 ,  H05K1/0284 ,  H05K1/0393 ,  H05K1/056 ,  H05K3/048 ,  H05K3/28 ,  H05K3/365 ,  H05K3/386 ,  H05K2201/0154 ,  H05K2203/066 ,  H05K2203/135

摘要： An assembly part for constituting a unit in a vacuum column is provided with wirings and wiring terminals. Each wiring is provided on a first insulating film, and is covered with a second insulating film made of an electro-deposited polyimide film. The assembly part is used to constitute a semiconductor manufacturing system such as an electron beam exposure system.

摘要翻译： 用于构成真空塔中的单元的组装部分设置有布线和布线端子。 每个布线设置在第一绝缘膜上，并被由电沉积聚酰亚胺膜制成的第二绝缘膜覆盖。 组装部分用于构成诸如电子束曝光系统的半导体制造系统

公开(公告)号：US06570169B2

公开(公告)日：2003-05-27

申请号：US10036453

申请日：2002-01-07

申请人： Kyoichi Suguro ,  Katsuya Okumura

发明人： Kyoichi Suguro ,  Katsuya Okumura

IPC分类号： H01J37317

CPC分类号： H01L21/26593 ,  H01J37/3171 ,  H01L21/26513 ,  H01L21/324

摘要： The purpose of the present invention is to avoid a decrease in the mechanical strength of a Si substrate because of the repetition of ion-implantation and annealing processes. As ions are implanted while the Si substrate surface temperature is kept at as low as −60° C. or less. Then the Si substrate is heated to recover the implantation defects caused by the ion-implantation. Such a combination of the low temperature ion-implantation and the annealing processes is repeated as required.

公开(公告)号：US06547638B2

公开(公告)日：2003-04-15

申请号：US09804232

申请日：2001-03-13

申请人： Katsuya Okumura ,  Riichirou Aoki ,  Hiromi Yajima ,  Seiji Ishikawa ,  Manabu Tsujimura

发明人： Katsuya Okumura ,  Riichirou Aoki ,  Hiromi Yajima ,  Seiji Ishikawa ,  Manabu Tsujimura

IPC分类号： B24B5100

CPC分类号： H01L21/67161 ,  B08B1/04 ,  B24B27/0023 ,  B24B37/04 ,  B24B37/345 ,  B24B51/00 ,  B24B55/12 ,  F24F3/161 ,  H01L21/67028 ,  H01L21/67046 ,  H01L21/67057 ,  H01L21/67167 ,  H01L21/67219 ,  H01L21/67745 ,  H01L21/67778 ,  H03M13/39 ,  H04N5/4401 ,  H04N5/455

摘要： A polishing apparatus includes an arrangement of a plurality of units to deal with various operations and a robot having at least one arm. The plurality of units are disposed around the robot and include a loading unit for receiving thereon a, e.g. dry, workpiece to be polished, a polishing system including at least one polishing unit for polishing the workpiece, a washing system and a drying system at least including one washing unit for washing and drying the polished workpiece, and an unloading unit for receiving thereon a resultant clean and dry polished workpiece.

公开(公告)号：US06525328B1

公开(公告)日：2003-02-25

申请号：US09624355

申请日：2000-07-24

申请人： Motosuke Miyoshi ,  Yuichiro Yamazaki ,  Katsuya Okumura

发明人： Motosuke Miyoshi ,  Yuichiro Yamazaki ,  Katsuya Okumura

IPC分类号： H01J3730

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  H01J37/3174

摘要： An electron beam lithography system 10 comprises an electron gun including a rectangular cathode 1 having an emission surface having an aspect ratio of other than 1, an illumination optical system 3 of an asymmetric lens system including multipole lenses Qa1 and Qa2, a CP aperture 5, and a projection optical system 8 of a symmetric lens system including multipole lenses Qb1 through Qb4. This electron beam lithography system 10 is used for emitting an electron beam at a low acceleration of 5 kV or less from the rectangular cathode 1, for controlling the illumination optical system so as to form an image of a desired character of the CP aperture 5 on an isotropic plane of incidence at different demagnifications in minor-axis and major-axis directions in accordance with the aspect ratio of the rectangular cathode 1, and for controlling the projection optical system 8 so that the electron beam leaving the CP aperture 5 as an aperture image is incident on a substrate 21 at the same demagnification in the minor-axis and major-axis directions and at different incident angles in the minor-axis and major-axis directions while passing through the trajectory without establishing any crossovers.

摘要翻译： 电子束光刻系统10包括电子枪，其包括具有不同于1的纵横比的发射表面的矩形阴极1，包括多极透镜Qa1和Qa2的非对称透镜系统的照明光学系统3，CP孔5， 以及包括多极透镜Qb1至Qb4的对称透镜系统的投影光学系统8。 该电子束光刻系统10用于从矩形阴极1以5kV以下的低加速度发射电子束，用于控制照明光学系统，以便形成CP孔5的所需字符的图像 根据矩形阴极1的纵横比在短轴和长轴方向上的不同缩小的各向同性平面，并且用于控制投影光学系统8，使得离开CP孔5的电子束作为孔 图像在短轴和长轴方向上以相同的缩小入射在基板21上，并且在短轴和长轴方向上以不同的入射角同时穿过轨迹而不建立任何交叉。

公开(公告)号：US06414499B2

公开(公告)日：2002-07-02

申请号：US09846372

申请日：2001-05-02

申请人： Hiroyuki Yano ,  Katsuya Okumura

发明人： Hiroyuki Yano ,  Katsuya Okumura

IPC分类号： G02R31308

CPC分类号： H01L22/26 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： An equipment for manufacturing semiconductor devices, comprises a processing tool which processes a to-be-processed surface of a semiconductor workpiece to a target shape, a monitor which three-dimensionally monitors a shape of a processed surface of the semiconductor workpiece while the semiconductor workpiece is set in the processing tool, and a controller which controls the processing tool in a feedback manner on the basis of the shape of the processed surface monitored by the monitor. If the shape of the processed surface deviates from the target shape, the controller adjusts process conditions of the processing tool so that the target shape can be obtained.

摘要翻译： 一种用于制造半导体器件的设备，包括将半导体工件的待处理表面处理为目标形状的处理工具，在半导体工件的三维监视半导体工件的加工表面的形状的监视器 设置在处理工具中，以及控制器，其基于由监视器监视的处理表面的形状以反馈方式控制处理工具。 如果处理后的表面的形状偏离目标形状，则控制器调整加工工具的工艺条件，从而可以获得目标形状。

公开(公告)号：US06368951B2

公开(公告)日：2002-04-09

申请号：US09903992

申请日：2001-07-13

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga ,  Akihiro Kajita ,  Tetsuo Matsuda ,  Tadashi Iijima ,  Hisashi Kaneko ,  Hideki Shibata ,  Naofumi Nakamura ,  Minakshisundaran Balasubramanian Anand ,  Tadashi Matsuno ,  Katsuya Okumura

IPC分类号： H01L214763

CPC分类号： H01L21/76852 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

摘要翻译： 一种半导体器件的制造方法，其特征在于，在形成于半导体衬底上的第一绝缘膜上形成沟槽，在所述沟槽中形成下层配线的工序，在所述半导体衬底上形成至少一层导体层， 在导电层上形成至少一层薄膜层的步骤，通过图案化薄膜形成硬掩模的步骤，通过使用硬掩模作为蚀刻掩模蚀刻导电层的步骤，以及形成 导电柱状结构，其上表面被硬掩模覆盖在下层布线上;在半导体基板上形成第二绝缘膜以使柱状结构被埋设的步骤，形成 至少暴露硬掩模的布线沟槽以及在去除硬掩模之后将导体埋入布线沟槽中的步骤，以及在布线沟槽中形成上层布线。

公开(公告)号：US06335534B1

公开(公告)日：2002-01-01

申请号：US09291967

申请日：1999-04-15

申请人： Kyoichi Suguro ,  Atsushi Murakoshi ,  Katsuya Okumura

发明人： Kyoichi Suguro ,  Atsushi Murakoshi ,  Katsuya Okumura

IPC分类号： H01J37317

CPC分类号： H01J37/3171 ,  H01J2237/31711

摘要： An electrically conductive mask having openings formed is located above a semiconductor substrate and ions are implanted into the surface of the semiconductor substrate through the electrically conductive mask, thereby forming ion implanted layers. For ion implantation under different conditions, a dedicated electrically conductive mask is used wit each ion implantation step.

摘要翻译： 具有形成开口的导电掩模位于半导体衬底之上，并且通过导电掩模将离子注入到半导体衬底的表面中，从而形成离子注入层。 对于在不同条件下的离子注入，每个离子注入步骤都使用专用的导电掩模。

公开(公告)号：US06284020B1

公开(公告)日：2001-09-04

申请号：US09555501

申请日：2000-06-02

申请人： Ayako Mizuno ,  Makiko Katano ,  Katsuya Okumura

发明人： Ayako Mizuno ,  Makiko Katano ,  Katsuya Okumura

IPC分类号： B01D5000

CPC分类号： H01L21/67366 ,  H01L21/67017 ,  H01L21/67393

摘要： A method of maintaining cleanliness of substrates including a first step for accommodating at least a piece of substrate having a gaseous impurity-trapping filter arranged close thereto in a hermetically sealed box, and a second step for circulating the atmosphere in the box at a rate of two or more times a minute so that impurities in the atmosphere are adsorbed by the gaseous impurity-trapping filter. A box for accommodating substrates includes a housing in which space for accommodating the substrates is hermetically closed with a lid, a gaseous impurity-trapping filter arranged in the housing and adapted to adsorb impurities contained in the atmosphere in space, and an atmosphere-circulating device having a ratio of the circulating capacity to the space volume of not smaller than 2 in order to circulate the atmosphere so as to pass it through the gaseous impurity-trapping filter.

摘要翻译： 一种保持基板的清洁的方法，包括：第一步骤，用于将至少一片具有靠近其设置的气态杂质捕获过滤器的基板容纳在气密密封的盒子中;第二步骤，用于使盒子中的气氛以 两次或更多次，使得大气中的杂质被气态杂质捕获过滤器吸附。 用于容纳基板的盒子包括壳体，其中容纳基板的空间用盖子气密地封闭，气体杂质捕获过滤器布置在壳体中并且适于吸收空间中包含的杂质，并且气氛循环装置 使循环容积与空间体积的比率不小于2，以使气氛循环，以使其通过气态杂质捕获过滤器。

公开(公告)号：US06239441B1

公开(公告)日：2001-05-29

申请号：US09007053

申请日：1998-01-14

申请人： Kyoichi Suguro ,  Katsuya Okumura

发明人： Kyoichi Suguro ,  Katsuya Okumura

IPC分类号： H01J37317

CPC分类号： H01L21/26593 ,  H01J37/3171 ,  H01L21/26513 ,  H01L21/324

摘要： The purpose of the present invention is to avoid a decrease in the mechanical strength of a Si substrate because of the repetition of ion-implantation and annealing processes. As ions are implanted while the Si substrate surface temperature is kept at as low as −60° C. or less. Then the Si substrate is heated to recover the implantation defects caused by the ion-implantation. Such a combination of the low temperature ion-implantation and the annealing processes is repeated as required.

摘要翻译： 本发明的目的是避免由于重复离子注入和退火过程而导致的Si衬底的机械强度降低。 当Si衬底表面温度保持在-60℃以下时，注入离子。 然后加热Si衬底以回收由离子注入引起的注入缺陷。 根据需要重复低温离子注入和退火处理的这种组合。