公开(公告)号：US20110252206A1

公开(公告)日：2011-10-13

申请号：US13008522

申请日：2011-01-18

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G06F12/02 ,  G11C11/00

CPC分类号： G11C7/1015 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0085 ,  G11C2013/0088

摘要： A memory system comprises a memory including a plurality of bits arranged as one or more words. Each bit in each word is capable of being programmed either to a particular logical state or to another logical state. A variable data width controller is in communication with the memory. The variable data width controller comprises an adder to determine a programming number of bits in a word to be programmed into a memory. Each bit to be programmed is in the particular logical state. A partitioning block divides the word in to two or more sub-words when the programming number exceeds a maximum number. A switch is in communication with the partitioning block. The switch sequentially provides one or more write pulses. Each write pulse enables a separate communication path between the memory and one of the word and the sub-words.

摘要翻译： 存储器系统包括存储器，该存储器包括排列成一个或多个单词的多个位。 每个单词中的每个位都能够被编程到特定的逻辑状态或另一个逻辑状态。 可变数据宽度控制器与存储器通信。 可变数据宽度控制器包括加法器，用于确定要编程到存储器中的一个字中的位的编程位数。 要编程的每个位处于特定的逻辑状态。 当编程号码超过最大数量时，划分块将字分成两个或多个子字。 开关与分区块通信。 开关依次提供一个或多个写入脉冲。 每个写入脉冲使得存储器与字和子字中的一个之间的单独通信路径成为可能。

公开(公告)号：US20110153974A1

公开(公告)日：2011-06-23

申请号：US13038997

申请日：2011-03-02

申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G06F12/00

CPC分类号： G06F13/4239 ,  G11C16/08 ,  G11C16/20 ,  G11C2216/30

摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.

摘要翻译： 提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。 存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。 每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。 每个存储器命令特定于目标存储器件的存储器类型。 存储器命令和存储器响应的数据路径由互连提供。 给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。 在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。 存储器响应被传送到存储器控制器。

公开(公告)号：US07908429B2

公开(公告)日：2011-03-15

申请号：US12832121

申请日：2010-07-08

申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G06F5/00

CPC分类号： G06F13/4243 ,  G06F13/4247

摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

公开(公告)号：US07818464B2

公开(公告)日：2010-10-19

申请号：US11567551

申请日：2006-12-06

申请人： Hong Beom Pyeon ,  HakJune Oh

发明人： Hong Beom Pyeon ,  HakJune Oh

IPC分类号： G06F3/00 ,  G06F13/00 ,  G11C8/10

CPC分类号： G11C5/066 ,  G06F13/1673 ,  G06F13/28 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/1093 ,  G11C2207/107

摘要： A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.

摘要翻译： 串行输入处理装置提供如何在命令解码器中以高频执行命令解释时捕获串行数据而不丢失单个位。 预定义序列的串行位的单个字节被锁存，并且使用多个时钟临时存储位流。 在将字节信息传送到分配的地址寄存器之前进行临时存储，以注册地址。 地址注册和数据登记是通过在时钟的前沿锁存串行输入的所有比特流来执行的。 在高频操作（例如，1GHz或1ns周期时间）期间，在命令解释期间，在命令比特流解释和下一比特数据流之间具有足够的时间余量，不需要额外的寄存器来存储比特数据。

公开(公告)号：US07774537B2

公开(公告)日：2010-08-10

申请号：US12030235

申请日：2008-02-13

申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G06F5/00

CPC分类号： G06F13/4243 ,  G06F13/4247

摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

摘要翻译： 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

公开(公告)号：US07719892B2

公开(公告)日：2010-05-18

申请号：US12179835

申请日：2008-07-25

申请人： Jin-Ki Kim ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  Hong Beom Pyeon

IPC分类号： G11C16/00

CPC分类号： G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

摘要： An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

摘要翻译： 公开了一种用于控制半导体存储器中的多个串行数据链路接口和多个存储体之间的数据传输的装置，系统和计算机实现的方法。 在一个示例中，公开了具有多个链路和存储体的闪存器件，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：US07602222B2

公开(公告)日：2009-10-13

申请号：US11238973

申请日：2005-09-30

申请人： Hong Beom Pyeon ,  Peter Vlasenko

发明人： Hong Beom Pyeon ,  Peter Vlasenko

IPC分类号： H03L7/00

CPC分类号： G06F1/24 ,  G06F1/3203 ,  H02J9/005

摘要： A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.

摘要翻译： 一种在省电模式下降低功耗的上电电路，同时保持表示电源电压令人满意的有效标志信号。 这是通过在省电模式期间关闭上电电路并且使用状态保持电路来响应于掉电信号来维持有效标志信号来实现的。 状态保持电路响应于上电电路的内部节点，以在内部节点达到预定电平时产生有效标志信号。 掉电信号可以是睡眠模式信号和深度掉电信号中的一个或两个。 状态保持包括用于将有效标志信号保持在省电模式中的超控电路，以及用于在省电模式退出时至少快速复位上电电路的内部节点的恢复电路。

公开(公告)号：US07593281B2

公开(公告)日：2009-09-22

申请号：US11781581

申请日：2007-07-23

申请人： Hong Beom Pyeon ,  Bruce Millar

发明人： Hong Beom Pyeon ,  Bruce Millar

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

摘要： A voltage down converter (VDC) applicable to high-speed memory devices. The VDC includes a steady driver and active driver along with at least one additional transistor. The steady driver and active driver are coupled by a transistor switch during device start-up to provide fast ramp-up to operating voltage and current. After start-up, the steady driver and active drive function to maintain a steady operating voltage and current. An additional transistor is digitally controlled to drive up operating voltage and current upon issuance of an active command representing read, write, and/or refresh of memory. In this manner, the additional transistor provides fast compensation for fluctuations in operating voltage and current brought on by activity in the memory array.

摘要翻译： 适用于高速存储器件的降压转换器（VDC）。 VDC包括一个稳定的驱动器和有源驱动器以及至少一个额外的晶体管。 稳定的驱动器和有源驱动器在器件启动期间由晶体管开关耦合，以提供对工作电压和电流的快速上升。 启动后，稳定的驱动器和主动驱动功能保持稳定的工作电压和电流。 在发出表示存储器的读取，写入和/或刷新的活动命令时，附加晶体管被数字控制以驱动工作电压和电流。 以这种方式，附加晶体管对存储器阵列中的活动引起的工作电压和电流的波动提供快速补偿。

公开(公告)号：US07577059B2

公开(公告)日：2009-08-18

申请号：US11711043

申请日：2007-02-27

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C7/10

CPC分类号： G11C16/08 ,  G11C8/12 ,  G11C8/20 ,  G11C16/16

摘要： Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks.

摘要翻译： 电路和方法用于控制闪存中的多页擦除操作。 多页擦除操作的每个地址的页面地址被锁存在字线解码器中。 页选择复位发生器电路处理多页擦除操作的每个地址的块地址。 在地址与不同块中的页面相关的情况下，先前锁存的页面地址被重置。 这样可以避免在多页擦除操作中包含不同块中的多个页面时导致的不正确的电路操作。

公开(公告)号：US07577029B2

公开(公告)日：2009-08-18

申请号：US11966152

申请日：2007-12-28

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C16/06 ,  G11C7/10

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5642 ,  G11C2211/5647

摘要： An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.

摘要翻译： 提供了使用两级MLC（多级单元）操作的诸如页面缓冲器的访问缓冲器，用于写入诸如Flash的非易失性存储器。 访问缓冲器具有用于临时存储要写入的数据的第一锁存器。 提供第二锁存器用于从作为两级写入操作的一部分的数据从存储器读取数据。 第二个锁存器具有从存储器读取时参与锁存功能的反相器。 相同的反相器用于产生正被写入第一锁存器的输入信号的补码，结果是使用双端输入来写入第一锁存器。