公开(公告)号：US06916698B2

公开(公告)日：2005-07-12

申请号：US10795672

申请日：2004-03-08

申请人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

发明人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

IPC分类号： H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC分类号： H01L21/823807 ,  H01L21/823828

摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

摘要翻译： 公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如 需要具有中间间隙金属栅极的CMOS器件。 本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间） ）以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。 对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

公开(公告)号：US20050148161A1

公开(公告)日：2005-07-07

申请号：US10751208

申请日：2004-01-02

申请人： Huajie Chen ,  Dan Mocuta ,  Richard Murphy ,  Stephan Bedell ,  Devendra Sadana

发明人： Huajie Chen ,  Dan Mocuta ,  Richard Murphy ,  Stephan Bedell ,  Devendra Sadana

IPC分类号： C30B25/02 ,  C30B29/06 ,  C30B29/52 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/36 ,  H01L21/44

CPC分类号： H01L21/02046 ,  C30B25/02 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02661 ,  Y10S438/933

摘要： The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×1013-1×1015/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process which heats the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface sufficiently to remove additional oxygen from the surface and leave a second amount of oxygen, less than the first amount, on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The heating process leaves an amount of at least 5×1012/cm2 of oxygen (typically, between approximately 1×1013/cm2 and approximately 5×1013/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. By leaving a small amount of oxygen on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.

公开(公告)号：US20050045947A1

公开(公告)日：2005-03-03

申请号：US10604907

申请日：2003-08-26

申请人： Huajie Chen ,  Bruce Doris ,  Philip Oldiges ,  Xinlin Wang ,  Huilong Zhu

发明人： Huajie Chen ,  Bruce Doris ,  Philip Oldiges ,  Xinlin Wang ,  Huilong Zhu

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/786 ,  H01L29/76 ,  H01L29/745 ,  H01L31/062

CPC分类号： H01L29/78696 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78684

摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. The devices have a thin channel, e.g., an ultra-thin (smaller than or equal to 10 nanometers (10 nm)) silicon on insulator (SOI) layer. Source/drain regions are located in recesses at either end of the thin channel and are substantially thicker (e.g., 30 nm) than the thin channel. Source/drain extensions and corresponding source/drain regions are self aligned to the FET gate and thin channel.

摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 器件具有薄沟道，例如超薄（小于或等于10纳米（10nm））绝缘体上硅（SOI）层。 源极/漏极区位于薄沟道的任一端的凹槽中，并且比薄沟道基本上更厚（例如，30nm）。 源/漏扩展和相应的源极/漏极区域与FET栅极和薄沟道自对准。

公开(公告)号：US06844225B2

公开(公告)日：2005-01-18

申请号：US10345469

申请日：2003-01-15

申请人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

发明人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

IPC分类号： H01L21/321 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L21/00

CPC分类号： H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.

摘要翻译： 使用不同材料的不同氧化速率形成自对准氧化物掩模。 自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。 通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。 通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及 在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在 多晶硅（或Si / siGe）。 然后在自对准掩模形成之后形成隆起的外在基体。 该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

公开(公告)号：US09502933B2

公开(公告)日：2016-11-22

申请号：US14235574

申请日：2011-08-31

申请人： Hui Huang ,  Yusheng Hu ,  Dongsuo Chen ,  Huajie Chen ,  Yong Xiao ,  Xueying Zeng ,  Wenming Zhang

发明人： Hui Huang ,  Yusheng Hu ,  Dongsuo Chen ,  Huajie Chen ,  Yong Xiao ,  Xueying Zeng ,  Wenming Zhang

IPC分类号： H02K1/27

CPC分类号： H02K1/2766

摘要： A permanent magnet synchronous electric machine includes a stator and a rotor. Multiple wire grooves are provided peripherally on the stator, coils are provided within the wire grooves, and a stator tooth is provided between adjacent wire grooves. Multiple magnetic groove sets are provided peripherally within the rotor, each of the magnetic groove sets includes at least two magnetic steel grooves, with permanent magnets placed within the magnetic steel grooves, and a magnetic tunnel formed between the magnetic steel grooves. Of two adjacent magnetic tunnels, an end of one magnetic tunnel is opposite a wire groove and an end of the other magnetic tunnel is opposite a stator tooth. The permanent magnet synchronous electric machine has a more steady output torque, and also reduces the noise and vibration provided during operation.

摘要翻译： 永磁同步电机包括定子和转子。 多个线槽周向设置在定子上，线圈设置在线槽内，定子齿设在相邻线槽之间。 在转子周围设有多个磁槽组，每个磁槽组包括至少两个磁钢槽，其中放置有磁钢槽内的永磁体，以及形成在磁钢槽之间的磁隧道。 在两个相邻的磁隧道中，一个磁通道的一端与电线槽相对，另一个磁通道的一端与定子齿相对。 永磁同步电机具有更稳定的输出转矩，并且还降低了运行中提供的噪声和振动。

公开(公告)号：US20140191607A1

公开(公告)日：2014-07-10

申请号：US14235604

申请日：2011-08-29

申请人： Hui Huang ,  Yusheng Hu ,  Dongsuo Chen ,  Huajie Chen ,  Yong Xiao ,  Xueying Zeng ,  Wenming Zhang

发明人： Hui Huang ,  Yusheng Hu ,  Dongsuo Chen ,  Huajie Chen ,  Yong Xiao ,  Xueying Zeng ,  Wenming Zhang

IPC分类号： H02K1/27

CPC分类号： H02K1/27 ,  H02K1/246 ,  H02K1/2766 ,  H02K2213/03

摘要： Disclosed is a motor rotor, comprising an iron core (10) and permanent magnets (20) provided inside the iron core (10). The iron core (10) is provided with sets of mounting grooves (30) on the iron core (10) in the peripheral direction of the iron core, each set of mounting grooves (30) comprising two or more mounting grooves (30) provided intermittently in the radial direction of the iron core (10). There are sets of permanent magnets (20), the individual permanent magnets (20) of each set of permanent magnets (20) correspondingly being embedded into the individual mounting grooves (30) of each set of mounting grooves; there is an island region (12) between the outermost layer of mounting grooves (30) and the periphery of the iron core (10), and an enhancing hole (13) is provided in the island region (12), an enhancing rod (60) being provided in the enhancing hole (13). Disclosed is a motor, comprising a motor stator (50) and the above-mentioned motor rotor, with the motor rotor provided inside the motor stator (50). The motor rotor enhances the structural strength of the whole rotor and improves the performance of the motor.

摘要翻译： 公开了一种电动机转子，包括设置在铁芯（10）内部的铁芯（10）和永磁体（20）。 铁芯（10）在铁芯的圆周方向上在铁芯（10）上设置有一组安装槽（30），每组安装槽（30）包括两个或更多个安装槽（30） 在铁芯（10）的径向方向间断地进行。 有一组永磁体（20），每组永磁体（20）的各个永久磁体（20）相应地嵌入每组安装槽的各个安装槽（30）中; 在安装槽（30）的最外层与铁芯（10）的外周之间具有岛状区域（12），在岛状区域（12）上设有增强孔（13），增强杆 60）设置在增强孔（13）中。 公开了一种电动机，其包括电动机定子（50）和上述电动机转子，电动机转子设置在电动机定子（50）的内部。 电机转子提高了整个转子的结构强度，提高了电机的性能。

公开(公告)号：US07767503B2

公开(公告)日：2010-08-03

申请号：US12132853

申请日：2008-06-04

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/84 ,  H01L21/336

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US07550370B2

公开(公告)日：2009-06-23

申请号：US10597066

申请日：2004-01-16

申请人： Huajie Chen ,  Stephen W. Bedell ,  Devendra K. Sadana ,  Dan M. Mocuta

发明人： Huajie Chen ,  Stephen W. Bedell ,  Devendra K. Sadana ,  Dan M. Mocuta

IPC分类号： H01L21/00

CPC分类号： H01L21/76256 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/31658 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/78687

摘要： A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550° C.-700° C.) HIPOX or steam oxidation, in-situ HCl etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCl, DCS and GeH4.

摘要翻译： 一种形成绝缘体上硅锗（SGOI）结构的方法。 SiGe层沉积在SOI晶片上。 进行SiGe和Si层的热混合以形成具有高松弛和低堆垛层错缺陷密度的厚SGOI。 然后将SiGe层变薄至所需的最终厚度。 稀释过程，Ge浓度，松弛量和堆垛层错缺陷密度均不变。 因此获得了具有高松弛和低堆垛层错缺陷密度的薄SGOI膜。 然后在薄SGOI晶片上沉积一层Si。 稀释方法包括低温​​（550℃-700℃）HIPOX或蒸汽氧化，在外延室中进行原位HCl蚀刻或CMP。 由HIPOX或蒸汽氧化稀化产生的粗糙SiGe表面在应变Si沉积期间用接触式CMP，原位氢气烘烤和SiGe缓冲层进行平滑，或者在氢气环境中用HCl，DCS混合气体加热晶片 和GeH4。

公开(公告)号：US20080242069A1

公开(公告)日：2008-10-02

申请号：US12132853

申请日：2008-06-04

申请人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US07381623B1

公开(公告)日：2008-06-03

申请号：US11623882

申请日：2007-01-17

申请人： Huajie Chen ,  Judson R. Holt ,  Kern Rim ,  Dominic J. Schepis

发明人： Huajie Chen ,  Judson R. Holt ,  Kern Rim ,  Dominic J. Schepis

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/331 ,  H01L21/36

CPC分类号： H01L21/823864 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.

摘要翻译： 本发明的实施例提供了一种用于具有非常低的温度选择性外延的预外延一次性间隔物集成方案的方法等，以增强器件性能。 更具体地，一种方法是通过在衬底上形成第一栅极和第二栅极开始的。 接下来，在第一和第二栅极上形成氧化物层; 并且在氧化物层上形成氮化物层。 接近第一栅极的氮化物层的部分，靠近第一栅极的氧化物层的部分以及靠近第一栅极的衬底的部分被去除，以便形成靠近第一栅极的源极和漏极。 接下来，该方法去除氮化物层的剩余部分，包括暴露氧化物层的剩余部分。 去除氮化物层的剩余部分仅暴露氧化物层和源极和漏极凹槽的剩余部分。