公开(公告)号：US20230197836A1

公开(公告)日：2023-06-22

申请号：US17557128

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Carl Hugo Naylor ,  Christopher J. Jezewski ,  Jeffery D. Bielefeld ,  Jiun-Ruey Chen ,  Ramanan V. CHEBIAM ,  Mauro J. Kobrinsky ,  Matthew V. Metz ,  Scott B. Clendenning ,  Sudurat Lee ,  Kevin P. O'Brien ,  Kirby Kurtis Maxey ,  Ashish Verma Penumatcha ,  Chelsey Jane Dorow ,  Uygar E. Avci

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7606 ,  H01L29/0665 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02568 ,  H01L29/401 ,  H01L29/66969

Abstract: Described herein are integrated circuit devices with conductive regions formed from MX or MAX materials. MAX materials are layered, hexagonal carbides and nitrides that include an early transition metal (M) and an A group element (A). MX materials remove the A group element. MAX and MX materials are highly conductive, and their two-dimensional layer structure allows very thin layers to be formed. MAX or MX materials can be used to form several conductive elements of IC circuits, including contacts, interconnects, or liners or barrier regions for contacts or interconnects.

公开(公告)号：US11646374B2

公开(公告)日：2023-05-09

申请号：US16232615

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Tanay Gosavi ,  Uygar Avci ,  Ian A. Young

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  G11C11/22 ,  H01L29/417 ,  H01L21/28

CPC classification number: H01L29/78391 ,  G11C11/223 ,  G11C11/2275 ,  H01L29/40111 ,  H01L29/41725 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

Abstract: Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11646356B2

公开(公告)日：2023-05-09

申请号：US16238419

申请日：2019-01-02

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/088 ,  H03H9/17 ,  H01L29/423

CPC classification number: H01L29/516 ,  H01L27/0886 ,  H01L29/42356 ,  H01L29/7851 ,  H01L29/78391 ,  H03H9/17

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

公开(公告)号：US11605624B2

公开(公告)日：2023-03-14

申请号：US16238421

申请日：2019-01-02

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01L27/02 ,  H01L49/02

Abstract: Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.

公开(公告)号：US20220199838A1

公开(公告)日：2022-06-23

申请号：US17133056

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Kevin O'Brien ,  Carl Naylor ,  Uygar Avci ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Chia-Ching LIn ,  Tanay Gosavi ,  Shriram Shivaraman ,  Kirby Maxey

IPC: H01L29/786 ,  H01L29/06 ,  H01L23/29 ,  H01L21/8238

Abstract: A transistor includes a channel layer including a transition metal dichalcogenide (TMD) material, an encapsulation layer on a first portion of the channel layer, a gate electrode above the encapsulation layer, a gate dielectric layer between the gate electrode and the encapsulation layer. The transistor further includes a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate structure is between drain contact and the source contact.

公开(公告)号：US20220102499A1

公开(公告)日：2022-03-31

申请号：US17032989

申请日：2020-09-25

Applicant: INTEL CORPORATION

Inventor： Carl Hugo Naylor ,  Kevin P. O'Brien ,  Chelsey Jane Dorow ,  Kirby Kurtis Maxey ,  Tanay Arun Gosavi ,  Ashish Verma Penumatcha ,  Urusa Shahriar Alaan ,  Uygar E. Avci

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/08 ,  H01L29/24

Abstract: Disclosed herein are transistors including two-dimensional materials, as well as related methods and devices. In some embodiments, a transistor may include a first two-dimensional channel material and a second two-dimensional source/drain (S/D) material in a source/drain (S/D), and the first two-dimensional material and the second two-dimensional material may have different compositions or thicknesses. In some embodiments, a transistor may include a first two-dimensional material in a channel and a second two-dimensional material in a source/drain (S/D), wherein the first two-dimensional material is a single-crystal material, and the second two-dimensional material is a single-crystal material.

公开(公告)号：US20210398993A1

公开(公告)日：2021-12-23

申请号：US16906217

申请日：2020-06-19

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Jack T. Kavalieros ,  Uygar E. Avci ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Devin R. Merrill ,  Matthew V. Metz ,  I-Cheng Tung

IPC: H01L27/11507 ,  H01L23/522 ,  H01L21/768

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

公开(公告)号：US20200286984A1

公开(公告)日：2020-09-10

申请号：US16296035

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Ashish Verma Penumatcha ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L49/02 ,  H01L27/108 ,  H01L27/11507

Abstract: Disclosed herein are capacitors with ferroelectric or antiferroelectric (FE/AFE) material and dielectric material, as well as related methods and devices. In some embodiments, a capacitor may include two electrodes, a layer of FE/AFE material between the electrodes, and a layer of dielectric material between the electrodes.

公开(公告)号：US20200286685A1

公开(公告)日：2020-09-10

申请号：US16294811

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L49/02 ,  H01L27/108

Abstract: Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.