公开(公告)号：US20190327132A1

公开(公告)日：2019-10-24

申请号：US16457100

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Sarig Livne ,  Ben-Zion Friedman ,  Noam Elati

IPC: H04L12/24 ,  H04W88/12 ,  H04W72/12 ,  G06F12/1027

Abstract: Technologies for performing dynamic configurations to a transmit scheduler of a network device with minimal downtime are disclosed. The transmit scheduler includes a topology of scheduling nodes. The transmit scheduler identifies, from a number of configuration operations to be executed on one or more of the scheduling nodes, one or more first configuration operations to be executed while the scheduling nodes are active, one or more second configuration operations to be executed while the scheduling nodes are inactive, and one or more third configuration operations to be executed via a cache. The first operations are executed as part of a background process. The second operations are executed while the scheduling nodes are inactive. The third operations are executed via the cache.

公开(公告)号：US20190042741A1

公开(公告)日：2019-02-07

申请号：US16142693

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Akeem Abodunrin ,  Lev Faerman ,  Scott Dubal ,  Suyog Kulkarni ,  Anjali Singhai Jain ,  Eliel Louzoun ,  Nrupal Jani ,  Yadong Li ,  Eliezer Tamir ,  Arvind Srinivasan ,  Ben-Zion Friedman

IPC: G06F21/55 ,  G06F13/40

Abstract: Technologies for control plane separation at a network interface controller (NIC) of a compute device configured to transmit, by a resource of the compute device, commands to a physical function managed by a network interface controller (NIC) of the compute device. The NIC is further to establish a data plane separate from a control plane, wherein the control plane comprises one of the trusted control path and the untrusted control path. Additionally, the resource is configured to transmit the commands via one of the trusted control path or the untrusted control path based on a trust level associated with the physical function. Other embodiments are described herein.

公开(公告)号：US20180322090A1

公开(公告)日：2018-11-08

申请号：US15584343

申请日：2017-05-02

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Ben-Zion Friedman

IPC: G06F15/173 ,  G06F11/14

CPC classification number: G06F15/17325 ,  G06F9/455 ,  G06F11/14 ,  G06F2201/815 ,  G06F2201/84 ,  H04L67/1002

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing system may include: a processor system including at least one first processor core having a first instruction set architecture (ISA); a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA; and control logic to suspend execution of the program by the at least one first processor core and cause at least one second processor core to resume execution of the program, wherein the at least one second processor core has a second ISA different from the first ISA; wherein the program is to generate data having an in-memory representation compatible with both the first ISA and the second ISA.

公开(公告)号：US20180173530A1

公开(公告)日：2018-06-21

申请号：US15387106

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Ben-Zion Friedman

IPC: G06F9/30 ,  G06F9/54 ,  G06F9/48

CPC classification number: G06F9/30025 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/48

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

公开(公告)号：US20180060246A1

公开(公告)日：2018-03-01

申请号：US15803244

申请日：2017-11-03

Applicant: Intel Corporation

Inventor： Ben-Zion Friedman ,  Jacob Doweck ,  Eliezer Weissmann ,  James B. Crossland ,  Ohad Falik

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

公开(公告)号：US20170353385A1

公开(公告)日：2017-12-07

申请号：US15626644

申请日：2017-06-19

Applicant: INTEL CORPORATION

Inventor： Eliezer Tamir ,  Ben-Zion Friedman

IPC: H04L12/721 ,  H04L12/805

CPC classification number: H04L45/72 ,  H04L47/36

Abstract: Examples are disclosed for forwarding or receiving data segments associated with a large data packets. In some examples, a large data packet may be segmented into a number of data segments having separate headers that include identifiers to associate the data segments with the large data packet. The data segments with separate headers may then be forwarded from a network node via a communication channel. In other examples, the data segments with separate headers may be received at another network node and then recombined to form the large data packet at the other network node. Other examples are described and claimed.

公开(公告)号：US20170249281A1

公开(公告)日：2017-08-31

申请号：US15289878

申请日：2016-10-10

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Ben-Zion Friedman ,  Steen Larsen

IPC: G06F15/173 ,  G06F13/42 ,  G06F3/06

CPC classification number: G06F15/17331 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0688 ,  G06F13/4282 ,  G06F15/167 ,  G06F21/44 ,  G06F21/79 ,  G06F21/80 ,  G06F2213/0026 ,  H04L67/1097 ,  H04L69/12 ,  Y02D10/14 ,  Y02D10/151

Abstract: Examples are disclosed for use of vendor defined messages to execute a command to access a storage device maintained at a server. In some examples, a network input/output device coupled to the server may receive the command from a client remote to the server for the client to access the storage device. For these examples, elements or components of the network input/output device may be capable of forwarding the command either directly to a Non-Volatile Memory Express (NVMe) controller that controls the storage device or to a manageability module coupled between the network input/out device and the NVMe controller. Vendor specific information may be forwarded with the command and used by either the NVMe controller or the manageability module to facilitate execution of the command. Other examples are described and claimed.

公开(公告)号：US09563431B2

公开(公告)日：2017-02-07

申请号：US14583308

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Ben-Zion Friedman

IPC: G06F9/00 ,  G06F9/38 ,  G06F9/46 ,  G06F1/32 ,  G06F13/00

CPC classification number: G06F9/3861 ,  G06F1/32 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/3802 ,  G06F9/3867 ,  G06F9/46 ,  G06F9/5038 ,  G06F9/5044 ,  Y02D10/122 ,  Y02D10/24 ,  Y02D50/20

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及用于较高功能核心和较低功率核心之间的协作的技术，以最小化中断对当前指令执行流的影响。 装置可以包括：包括第一指令流水线的下功率核心，低功率核心，用于停止第一指令流水线中的第一执行流程，并且执行第一指令流水线中的处理程序例程的指令，以执行第一任务处理 打断; 以及包括第二指令流水线的较高功能核心，所述较高功能核心在执行所述第一任务之后，调度在所述第二指令流水线中处理所述中断的第二任务的指令的执行，以遵循第二指令流程 第二条指令管道，第一个任务比第二个任务更时间敏感。 描述和要求保护其他实施例。

公开(公告)号：US09164917B2

公开(公告)日：2015-10-20

申请号：US14455147

申请日：2014-08-08

Applicant: Intel Corporation

Inventor： Ohad Falik ,  Ben-Zion Friedman ,  Jacob Doweck ,  Eliezer Weissmann ,  James B Crossland

IPC: G06F12/00 ,  G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract translation: 本发明的实施例一般涉及用于线性到物理地址转换的系统，方法和装置，其支持页面属性。 在一些实施例中，系统接收将存储器指针转换为存储器位置的物理存储器地址的指令。 系统可以返回物理内存地址和一个或多个页面属性。 描述和要求保护其他实施例。

公开(公告)号：US09081709B2

公开(公告)日：2015-07-14

申请号：US14258966

申请日：2014-04-22

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Eliel Louzon ,  Ben-Zion Friedman ,  Miles J. Penner

IPC: G06F3/00 ,  G06F13/10 ,  G06F9/44 ,  G06F9/46 ,  G06F9/54 ,  G06F3/06

CPC classification number: G06F13/105 ,  G06F9/4411 ,  G06F9/468 ,  G06F9/545 ,  G06F9/546 ,  G06F2003/0697

Abstract: Methods and apparatus are disclosed for virtualizable, forward-compatible hardware-software interfaces. Embodiments may be used in a driver whether it is a physical driver or a virtual driver. Commands are queued from the driver and fetched to the device. An actions table is accessed to determine if drivers are permitted to perform commands. Events are queued for the drivers responsive to commands. If drivers are not permitted to perform a command, device firmware may forward the command to a privileged driver to perform the required command. If a driver is only permitted to perform a command with assistance the command is forwarded for corrections and execution. If a command is to be dropped, a completion event may be queued as if the command had executed. Drivers may have no indication of which actions were taken. The actions table may be changed for hardware/software modifications or dynamically according to configuration changes.

Abstract translation: 公开了用于可虚拟化，前向兼容的硬件 - 软件接口的方法和装置。 驱动器中可以使用实施例，无论其是物理驱动器还是虚拟驱动器。 命令从驱动程序排队并提取到设备。 访问一个动作表以确定是否允许驱动程序执行命令。 事件针对响应于命令的驱动程序排队等候。 如果驱动程序不允许执行命令，则设备固件可将命令转发给特权驱动程序以执行所需的命令。 如果仅允许驱动程序执行命令，则该命令将被转发以进行更正和执行。 如果要删除命令，则完成事件可能会像命令执行一样排队。 司机可能没有指出采取了哪些行动。 可以针对硬件/软件修改或动态地根据配置更改来更改动作表。