公开(公告)号：US20190131437A1

公开(公告)日：2019-05-02

申请号：US16095655

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Van Hoang LE ,  Gilbert William DEWEY ,  Marko RADOSAVLJEVIC ,  Rafael RIOS ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L29/06 ,  H01L29/24

Abstract: Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.

公开(公告)号：US20190058053A1

公开(公告)日：2019-02-21

申请号：US15770628

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Seiyon KIM ,  Benjamin CHU-KUNG

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66583 ,  H01L29/0607 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/267 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7854

Abstract: Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.

公开(公告)号：US20180366587A1

公开(公告)日：2018-12-20

申请号：US15777117

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Kent E. MILLARD ,  Marc C. FRENCH ,  Ashish AGRAWAL ,  Benjamin CHU-KUNG ,  Ryan E. ARCH

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20180337235A1

公开(公告)日：2018-11-22

申请号：US15776996

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： WILLY RACHMADY ,  MATTHEW V. METZ ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  NADIA M. RAHHAL-ORABI ,  Jack T. KAVALIEROS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The subfin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20180331195A1

公开(公告)日：2018-11-15

申请号：US15773894

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Benjamin CHU-KUNG ,  Van H. LE ,  Gilbert DEWEY ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/47 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/47 ,  H01L21/28255 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/78

Abstract: An apparatus including a substrate; a transistor device on the substrate including a channel and a source and a drain disposed between the channel; a source contact coupled to the source and a drain contact coupled to the drain; and the source and drain each including a composition including a concentration of germanium at an interface with the channel that is greater than a concentration of germanium at a junction with the source contact. A method including defining an area on a substrate for a transistor device; forming a source and a drain each including an interface with the channel; and forming a contact to one of the source and the drain, wherein a composition of each of the source and the drain includes a concentration of germanium at an interface with the channel that is greater than a concentration at a junction with the contact.

公开(公告)号：US20180261669A1

公开(公告)日：2018-09-13

申请号：US15892182

申请日：2018-02-08

Applicant: Intel Corporation

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Harold Hal W. KENNEL ,  Willy RACHMADY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/15

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and mitigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

公开(公告)号：US20180158927A1

公开(公告)日：2018-06-07

申请号：US15575810

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Glenn A. GLASS ,  Willy RACHMADY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Matthew V. METZ

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66522 ,  B82Y10/00 ,  H01L21/02395 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30612 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, a multi-layer stack is formed by selectively depositing the entire epi-stack in an STI trench. The channel layer is grown pseudomorphically over a buffer layer. A cap layer is grown on top of the channel layer. In an embodiment, the height of the STI layer remains higher than the channel layer until the formation of the gate. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.

公开(公告)号：US20170012126A1

公开(公告)日：2017-01-12

申请号：US15119674

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Van H. LE ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Sansaptak DASGUPTA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Abstract translation: 描述了具有选择性再生长顶端触点的垂直半导体器件和制造具有选择性再生长顶端触点的垂直半导体器件的方法。 例如，半导体器件包括具有表面的衬底。 第一源极/漏极区域设置在衬底的表面上。 垂直沟道区域设置在第一源极/漏极区域上并且具有与衬底的表面平行的第一宽度。 第二源极/漏极区域设置在垂直沟道区域上并且具有与第一宽度平行并且基本上大于第一宽度的第二宽度。 栅堆叠设置在垂直沟道区的一部分上并完全环绕。

公开(公告)号：US20160240671A1

公开(公告)日：2016-08-18

申请号：US14914847

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Benjamin CHU-KUNG ,  Roza KOTLYAR

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7842 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/512 ,  H01L29/66439 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696

Abstract: An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.

Abstract translation: 一种包括设置在衬底上并限定沟道区的异质结构的装置，所述异质结构包括具有小于所述衬底的材料的带隙的第一带隙的第一材料和具有大于所述衬底的材料的第二带隙的第二材料 第一个带隙; 以及栅极堆叠，其中所述第二材料设置在所述第一材料和所述栅极叠层之间。 一种方法，包括在基板上形成具有第一带隙的第一材料; 形成具有大于所述第一材料上的所述第一带隙的第二带隙的第二材料; 以及在所述第二材料上形成栅叠层。

公开(公告)号：US20240224536A1

公开(公告)日：2024-07-04

申请号：US18090807

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Wilfred GOMES

IPC: H10B51/30

CPC classification number: H10B51/30

Abstract: Structures having layer select transistors for shared peripherals in memory are described. In an example, an integrated circuit structure includes a memory structure layer including a capacitor array coupled to a plurality of plate lines. A memory transistor layer is beneath the memory structure layer, the memory transistor layer including front end transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer. A select transistor layer is over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end transistors. One or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.