公开(公告)号：US09832863B2

公开(公告)日：2017-11-28

申请号：US14866614

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Shawna Liff

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/22 ,  H05K3/30 ,  H05K1/03

CPC classification number: H05K1/028 ,  H05K1/0283 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/118 ,  H05K1/181 ,  H05K3/22 ,  H05K3/284 ,  H05K3/301 ,  H05K3/4691 ,  H05K2201/05 ,  H05K2201/057 ,  H05K2201/09263 ,  H05K2201/095 ,  H05K2203/1316

Abstract: Some forms relate to a stretchable computing device that includes a stretchable body; a first electronic component embedded within the stretchable body; a second electronic component embedded within the stretchable body; and wherein the first electronic component and the second electronic component are connected by stretchable electrical connectors that include vias. The stretchable electrical connectors are non-planar and/or may have a partial zig-zag shape and/or a partial coil shape. In some forms, the stretchable computing device further includes a textile attached to the stretchable body.

公开(公告)号：US12288746B2

公开(公告)日：2025-04-29

申请号：US16727747

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Mauro Kobrinsky ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast ,  Sathya Narasimman Tiagaraj

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

公开(公告)号：US12272656B2

公开(公告)日：2025-04-08

申请号：US18380022

申请日：2023-10-13

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US12266840B2

公开(公告)日：2025-04-01

申请号：US17359138

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Johanna Swan ,  Adel Elsherbini ,  Shawna Liff ,  Beomseok Choi ,  Qiang Yu

IPC: H01P3/16 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01P1/208 ,  H01P5/107

Abstract: Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.

公开(公告)号：US12199048B2

公开(公告)日：2025-01-14

申请号：US18397915

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20240063091A1

公开(公告)日：2024-02-22

申请号：US17891735

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Scot Kellar ,  Yoshihiro Tomita ,  Rajiv Mongia ,  Kimin Jun ,  Shawna Liff ,  Wenhao Li ,  Johanna Swan ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Haris Khan Niazi ,  Jiraporn Seangatith ,  Thomas Sounart

IPC: H01L23/473 ,  H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L23/473 ,  H01L24/08 ,  H01L25/0652 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3677 ,  H01L23/3675 ,  H01L23/3732 ,  H01L23/3738 ,  H01L2924/3511 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/182 ,  H01L2924/186

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.

公开(公告)号：US20240063072A1

公开(公告)日：2024-02-22

申请号：US17891530

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Shawna Liff ,  Kimin Jun ,  Veronica Strong ,  Aleksandar Aleksov ,  Jiraporn Seangatith ,  Mohammad Enamul Kabir ,  Johanna Swan ,  Tushar Talukdar ,  Omkar Karhade

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/3135 ,  H01L25/0652 ,  H01L25/0655 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/291 ,  H01L24/08

Abstract: Composite integrated circuit (IC) device processing, including selective removal of inorganic dielectric material. Inorganic dielectric material may be deposited, modified with laser exposure, and selectively removed. Laser exposure parameters may be adjusted using surface topography measurements. Inorganic dielectric material removal may reduce surface topography. Vias and trenches of varying size, shape, and depth may be concurrently formed without an etch-stop layer. A composite IC device may include an IC die, a conductive via, and a conductive line adjacent a compositionally homogenous inorganic dielectric material.

公开(公告)号：US20240006332A1

公开(公告)日：2024-01-04

申请号：US17856801

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Dimitrios Antartis ,  Nitin A. Deshpande ,  Siyan Dong ,  Omkar Karhade ,  Gwang-soo Kim ,  Shawna Liff ,  Siddhartha Mal ,  Debendra Mallik ,  Khant Minn ,  Haris Khan Niazi ,  Arnab Sarkar ,  Yi Shi ,  Botao Zhang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/544 ,  H01L24/08 ,  H01L23/481 ,  H01L2224/08145 ,  H01L2223/54426

Abstract: An integrated circuit (IC) device comprises a host component and an IC die directly bonded to the host component. The IC die comprises a substrate material layer and a die metallization level between the substrate material layer and host component. The IC die includes an upper die alignment fiducial between the die metallization level and host component. The upper die alignment fiducial at least partially overlaps one or more metallization features within the die metallization level. In embodiments, at least two orthogonal edges of the upper die alignment fiducial do not overlap any of the metallization features within the die metallization level. In embodiments, the IC die includes a lower die alignment fiducial between the substrate material layer and the die metallization level. The lower die alignment fiducial may at least partially overlap one or more second metallization features within a second die metallization level of the IC die.

公开(公告)号：US11735533B2

公开(公告)日：2023-08-22

申请号：US16437254

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20220415743A1

公开(公告)日：2022-12-29

申请号：US17358361

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Aleksandar Aleksov ,  Julien Sebot

IPC: H01L23/36 ,  H01L25/065 ,  H01L21/50 ,  H01L27/06 ,  H01L23/00

Abstract: Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.