公开(公告)号：US20150327366A1

公开(公告)日：2015-11-12

申请号：US14807336

申请日：2015-07-23

Applicant: Intermolecular Inc.

Inventor： Mohd Fadzli Anwar Hassan ,  Guowen Ding ,  Minh Huu Le ,  Minh Anh Anh Nguyen ,  Zhi-Wen Wen Sun ,  Guizhen Zhang

IPC: H05K1/09 ,  H05K1/02

CPC classification number: H05K1/092 ,  C23C28/42 ,  C23C30/00 ,  H01L51/0097 ,  H01L51/5234 ,  H05K1/0274 ,  Y10T428/265

Abstract: Methods for making conducting stacks includes forming a doped or alloyed silver layer sandwiched between two layers of transparent conductive oxide such as indium tin oxide (ITO). The doped silver or silver alloy layer can be thin, such as between 1.5 to 20 nm and thus can be transparent. The doped silver or silver alloy can provide improved ductility property, allowing the conductive stack to be bendable. The transparent conductive oxide layers can also be thin, allowing the conductive stack can have improved ductility property.

Abstract translation: 制造导电叠层的方法包括形成夹在两层透明导电氧化物（例如氧化铟锡（ITO））之间的掺杂或合金化的银层。 掺杂的银或银合金层可以是薄的，例如在1.5至20nm之间，因此可以是透明的。 掺杂的银或银合金可以提供改善的延展性，允许导电叠层可弯曲。 透明导电氧化物层也可以是薄的，使得导电叠层可以具有改善的延展性。

公开(公告)号：US09177876B2

公开(公告)日：2015-11-03

申请号：US14105797

申请日：2013-12-13

Applicant: Intermolecular, Inc.

Inventor： Haifan Liang ,  Jessica Eid ,  Minh Huu Le ,  Jeroen Van Duren

IPC: H01L21/66 ,  H01L31/032 ,  H01L31/0749

CPC classification number: H01L22/12 ,  H01L31/0322 ,  H01L31/0749 ,  H01L2924/0002 ,  Y02E10/541 ,  Y02P70/521 ,  H01L2924/00

Abstract: Optical absorbers and methods are disclosed. The methods comprise depositing a plurality of precursor layers comprising one or more of Cu, Ga, and In on a substrate, and heating the layers in a chalcogenizing atmosphere. The plurality of precursor layers can be one or more sets of layers comprising at least two layers, wherein each layer in each set of layers comprises one or more of Cu, Ga, and In exhibiting a single phase. The layers can be deposited using two or three targets selected from Ag and In containing less than 21% In by weight, Cu and Ga where the Cu and Ga target comprises less than 45% Ga by weight, Cu(In,Ga), wherein the Cu(In,Ga) target has an atomic ratio of Cu to (In+Ga) greater than 2 and an atomic ratio of Ga to (Ga+In) greater than 0.5, elemental In, elemental Cu, and In2Se3 and In2S3.

Abstract translation: 公开了光吸收剂和方法。 所述方法包括在衬底上沉积包含Cu，Ga和In中的一种或多种的多个前体层，并在硫属化气氛中加热层。 多个前体层可以是包括至少两个层的一组或多组层，其中每组层中的每个层包括一个或多个Cu，Ga和In，其表现出单相。 这些层可以使用选自Ag和In的两个或三个靶，其中Cu和Ga的重量比小于45重量％的Cu（In，Ga）含有小于21重量％的Cu和Ga，其中Cu和 Cu（In，Ga）靶的Cu与（In + Ga）的原子比大于2，Ga与（Ga + In）的原子比大于0.5，元素In，元素Cu，In2Se3和In2S3。

公开(公告)号：US20150177585A1

公开(公告)日：2015-06-25

申请号：US14135462

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Guowen Ding ,  Minh Huu Le

IPC: G02F1/15 ,  C23C16/40

CPC classification number: G02F1/1523

Abstract: Disclosed herein are systems, methods, and apparatus for forming adjustable windows may include a substrate and a first conducting oxide layer formed over the substrate. The adjustable windows may further include a spectral tuning layer formed over the first conducting oxide layer and an ion conductor layer formed over the spectral tuning layer. The adjustable windows may also include an ion storage layer formed over the ion conductor layer and a second conducting oxide layer formed over the ion storage layer. In some embodiments, the spectral tuning layer may be configured to change an infrared transmissivity of the adjustable window. Furthermore, the spectral tuning layer may be configured to toggle a solar heat gain ratio coefficient of the adjustable window between two or more solar heat gain ratio coefficients.

Abstract translation: 本文公开了用于形成可调节窗口的系统，方法和装置可以包括衬底和形成在衬底上的第一导电氧化物层。 可调窗可进一步包括在第一导电氧化物层上形成的光谱调谐层和在光谱调谐层上形成的离子导体层。 可调节窗口还可以包括形成在离子导体层上的离子存储层和形成在离子存储层上的第二导电氧化物层。 在一些实施例中，频谱调谐层可以被配置为改变可调窗口的红外透射率。 此外，频谱调谐层可以被配置为在两个或多个太阳能热增益比系数之间切换可调整窗口的太阳能热增益系数。

公开(公告)号：US09012261B2

公开(公告)日：2015-04-21

申请号：US14094379

申请日：2013-12-02

Applicant: Intermolecular, Inc.

Inventor： Jeroen Van Duren ,  Sang Lee ,  Minh Huu Le ,  Sandeep Nijhawan ,  Teresa B. Sapirman

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/306 ,  H01L21/02 ,  H01L21/465 ,  H01L21/70 ,  H01L27/12

CPC classification number: H01L21/30604 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/32134 ,  H01L21/465 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract translation: 将HPC技术的方法应用于基板上的位置隔离区域（SIR）的处理，以形成在显示应用中使用的TFT器件的至少一部分。 该处理可以应用于栅电极沉积，栅极电极图案化，栅极介电沉积，栅极电介质图案化，金属基半导体材料（例如IGZO）沉积，金属基半导体材料（例如IGZO）图案化，蚀刻停止 沉积，蚀刻停止构图，源极/漏极沉积，源极/漏极图案化，钝化沉积或钝化图案化。 可以在沉积过程期间限定SIR，每个SIR内均匀沉积，或者可以在层的沉积之后定义SIR，其中层以跨越衬底的一个或多个特性的梯度沉积。

公开(公告)号：US20150093500A1

公开(公告)日：2015-04-02

申请号：US14136125

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Teresa B. Sapirman ,  Jianhua Hu ,  Minh Huu Le

IPC: H01B13/00

CPC classification number: H01L33/405 ,  H01L2933/0016

Abstract: The electrical and optical performance of silver LED reflective contacts in III-V devices such as GaN LEDs is limited by silver's tendency to agglomerate during annealing processes and to corrode on contact with silver-reactive materials elsewhere in the device (for example, gallium or aluminum). Agglomeration and reaction are prevented, and crystalline morphology of the silver layer may be optimized, by forming a diffusion-resistant transparent conductive layer between the silver and the source of silver-reacting metal, (2) doping the silver or the diffusion-resistant transparent conductive layer for improved adhesion to adjacent layers, or (3) doping the silver with titanium, which in some embodiments prevents agglomeration and promotes crystallization of the silver in the preferred orientation.

Abstract translation: III-V器件如GaN LED中的银LED反射触点的电学和光学性能受到退火过程中银的凝聚趋势的限制，并且与器件其他地方的银反应性材料（例如，镓或铝 ）。 防止聚集和反应，通过在银和银反应金属的源之间形成耐扩散的透明导电层，可以优化银层的结晶形态，（2）掺杂银或扩散阻挡的透明 导电层，用于改善与相邻层的粘附性，或（3）用钛掺杂银，在一些实施方案中，该银防止聚集并促进优选<111>取向的银的结晶。

公开(公告)号：US20150060910A1

公开(公告)日：2015-03-05

申请号：US14014029

申请日：2013-08-29

Applicant: Intermolecular Inc.

Inventor： Guowen Ding ,  Jianhua Hu ,  Minh Huu Le

IPC: H01L33/46 ,  H01L33/42

CPC classification number: H01L33/405 ,  H01L33/42

Abstract: Methods to improve the reflection of light emitting devices are disclosed. A method consistent with the present disclosure includes forming a light generating layer over a site-isolated region of a substrate. Next, forming a first transparent conductive layer over the light generating layer. Forming a low refractive index material over the first transparent conductive layer, and in time, forming a second transparent conductive layer over the low refractive index material. Subsequently, forming a reflective material layer thereon. Accordingly, methods consistent with the present disclosure may form a plurality of light emitting devices in various site-isolated regions on a substrate.

Abstract translation: 公开了改善发光器件反射的方法。 与本公开一致的方法包括在衬底的位置隔离区域上形成发光层。 接着，在光生成层上形成第一透明导电层。 在第一透明导电层上形成低折射率材料，并在时间上在低折射率材料上形成第二透明导电层。 随后，在其上形成反射材料层。 因此，与本公开一致的方法可以在衬底上的各种位置隔离区域中形成多个发光器件。

公开(公告)号：US20140308528A1

公开(公告)日：2014-10-16

申请号：US14144828

申请日：2013-12-31

Applicant: Intermolecular Inc.

Inventor： Guowen Ding ,  Brent Boyce ,  Jeremy Cheng ,  Jose Ferreira ,  Muhammad Imran ,  Minh Huu Le ,  Daniel Schweigert ,  Yu Wang ,  Yongli Xu ,  Guizhen Zhang

IPC: C23C14/10 ,  C03C17/34 ,  C23C14/34

CPC classification number: C03C17/366 ,  C03C17/3435 ,  C03C17/36 ,  C03C17/3613 ,  C03C17/3618 ,  C03C17/3626 ,  C03C17/3639 ,  C03C17/3644 ,  C03C17/3681 ,  C03C25/226 ,  C03C2218/155 ,  C23C14/0036 ,  C23C14/0652 ,  C23C14/0688 ,  C23C14/083 ,  C23C14/086

Abstract: Disclosed herein are systems, methods, and apparatus for forming a low emissivity panel. In various embodiments, a partially fabricated panel may be provided. The partially fabricated panel may include a substrate, a reflective layer formed over the substrate, and a top dielectric layer formed over the reflective layer such that the reflective layer is formed between the substrate and the top dielectric layer. The top dielectric layer may include tin having an oxidation state of +4. An interface layer may be formed over the top dielectric layer. A top diffusion layer may be formed over the interface layer. The top diffusion layer may be formed in a nitrogen plasma environment. The interface layer may substantially prevent nitrogen from the nitrogen plasma environment from reaching the top dielectric layer and changing the oxidation state of tin included in the top dielectric layer.

Abstract translation: 本文公开了用于形成低发射率面板的系统，方法和装置。 在各种实施例中，可以提供部分制造的面板。 部分制造的面板可以包括衬底，在衬底上形成的反射层，以及形成在反射层上的顶部电介质层，使得反射层形成在衬底和顶部电介质层之间。 顶部电介质层可以包括具有+4的氧化态的锡。 界面层可以形成在顶部介电层上。 可以在界面层上形成顶部扩散层。 顶部扩散层可以在氮等离子体环境中形成。 界面层可以基本上防止来自氮等离子体环境的氮到达顶部电介质层并改变顶部电介质层中包含的锡的氧化态。

公开(公告)号：US20140273340A1

公开(公告)日：2014-09-18

申请号：US14094379

申请日：2013-12-02

Applicant: Intermolecular, Inc.

Inventor： Jeroen Van Duren ,  Sang Lee ,  Minh Huu Le ,  Sandeep Nijhawan ,  Teresa B. Sapirman

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L21/30604 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/32134 ,  H01L21/465 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.

Abstract translation: 将HPC技术的方法应用于基板上的位置隔离区域（SIR）的处理，以形成在显示应用中使用的TFT器件的至少一部分。 该处理可以应用于栅电极沉积，栅极电极图案化，栅极介电沉积，栅极电介质图案化，金属基半导体材料（例如IGZO）沉积，金属基半导体材料（例如IGZO）图案化，蚀刻停止 沉积，蚀刻停止构图，源极/漏极沉积，源极/漏极图案化，钝化沉积或钝化图案化。 可以在沉积过程期间限定SIR，每个SIR内均匀沉积，或者可以在层的沉积之后定义SIR，其中层以跨越衬底的一个或多个特性的梯度沉积。

公开(公告)号：US20140272454A1

公开(公告)日：2014-09-18

申请号：US13801635

申请日：2013-03-13

Applicant: INTERMOLECULAR INC.

Inventor： Guizhen Zhang ,  Jeremy Cheng ,  Guowen Ding ,  Minh Huu Le ,  Daniel Schweigert ,  Yu Wang

IPC: C03C17/36 ,  C23C14/14

CPC classification number: C23C14/22 ,  C03C17/36 ,  C03C17/3605 ,  C03C17/3618 ,  C03C17/3644 ,  C03C17/3652 ,  C03C17/366 ,  C03C17/3681 ,  C23C14/0036 ,  C23C14/042 ,  C23C14/14 ,  C23C14/34 ,  G02B1/12 ,  G02B1/14 ,  Y10T428/12542 ,  Y10T428/12549 ,  Y10T428/12611 ,  Y10T428/12778 ,  Y10T428/31678

Abstract: Provided is High Productivity Combinatorial (HPC) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors. The tested barrier layers may include all or at least two of nickel, chromium, titanium, and aluminum. In some embodiments, the barrier layers include oxygen. This combination allows using relative thin barrier layers (e.g., 5-30 Angstroms thick) that have high transparency yet provide sufficient protection to the silver reflector. The amount of nickel in a barrier layer may be 5-10% by weight, chromium—25-30%, titanium and aluminum—30%-35% each. The barrier layer may be co-sputtered in a reactive or inert-environment using one or more targets that include all four metals. An article may include multiple silver reflectors, each having its own barrier layer.

Abstract translation: 提供了半导体衬底的高生产率组合（HPC）测试方法，每个包括多个现场隔离区域。 位置隔离区域用于测试布置在银反射器上的阻挡层的不同组成和/或结构。 经测试的阻挡层可以包括镍，铬，钛和铝中的全部或至少两种。 在一些实施例中，阻挡层包括氧。 该组合允许使用具有高透明度的相对薄的阻挡层（例如5-30埃厚），同时为银反射器提供足够的保护。 阻挡层中的镍的量可以是5-10重量％，铬25-30％，钛和铝30％-35％。 阻挡层可以在反应性或惰性环境中使用包括所有四种金属的一种或多种目标共溅射。 物品可以包括多个银反射器，每个具有其自己的阻挡层。

公开(公告)号：US20140272390A1

公开(公告)日：2014-09-18

申请号：US13834261

申请日：2013-03-15

Applicant: INTERMOLECULAR INC.

Inventor： Guowen Ding ,  Brent Boyce ,  Minh Huu Le ,  Zhi-Wen Wen Sun ,  Yu Wang

IPC: C03C17/36

CPC classification number: C03C17/366 ,  C03C17/36 ,  C03C17/3626 ,  C03C17/3644 ,  Y10T428/265

Abstract: Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A reflective layer is formed above the transparent substrate. A barrier layer is formed above the reflective layer. A nitride-containing layer is formed above the barrier layer. The nitride-containing layer has a thickness that is 1 nm or less. A over-coating layer is formed above the nitride-containing layer. The over-coating layer includes a different material than that of the nitride-containing layer.

Abstract translation: 本文提供的实施例描述了用于形成低e板的低e板和方法。 提供透明基板。 在透明基板的上方形成反射层。 在反射层上形成阻挡层。 在阻挡层上方形成含氮化物层。 含氮化物层的厚度为1nm以下。 在含氮化物层的上方形成覆盖层。 覆盖层包括与含氮化物层不同的材料。