公开(公告)号：US10558519B2

公开(公告)日：2020-02-11

申请号：US15407465

申请日：2017-01-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Glenn D. Gilda ,  Patrick J. Meaney

IPC: G06F11/10 ,  G06F11/14 ,  G06F3/06 ,  G06F1/3234

Abstract: Embodiments include techniques used for a power-reduced redundant array of independent memory RAIM system. The technique includes blocking commands to one or more memory modules of the RAIM system and reading data from one or more unblocked memory modules. The technique also includes applying a power channel mark for one or more blocked memory modules, the power channel mark indicating the one or more blocked memory modules to a decoder for error correction.

公开(公告)号：US10541782B2

公开(公告)日：2020-01-21

申请号：US15817416

申请日：2017-11-20

Applicant: International Business Machines Corporation

Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

IPC: H04L1/00 ,  H03M13/09

Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

公开(公告)号：US10419035B2

公开(公告)日：2019-09-17

申请号：US15817399

申请日：2017-11-20

Applicant: International Business Machines Corporation

Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

IPC: H03M13/00 ,  H03M13/35 ,  H04L1/00

Abstract: Aspects of the invention include calculating, by a transmitter, source cyclic redundancy code (CRC) bits for payload bits. The source CRC bits include source CRC bits for a first type of CRC check and source CRC bits for a second type of CRC check. The source CRC bits are stored at the transmitter. The payload bits and the source CRC bits for the first type of CRC check are transmitted to the receiver. The receiver performs the first type of CRC check based at least in part on the payload bits and the source CRC bits for the first type of CRC check. The receiver also calculates and stores at the receiver calculated CRC bits for the second type of CRC check. If the first type of CRC check indicates an error, a comparison of the source and calculated CRC bits for the second type of CRC check is initiated.

公开(公告)号：US10395698B2

公开(公告)日：2019-08-27

申请号：US15825894

申请日：2017-11-29

Applicant: International Business Machines Corporation

Inventor： Steven R. Carlough ,  Susan M. Eickhoff ,  Warren E. Maule ,  Patrick J. Meaney ,  Stephen J. Powell ,  Gary A. Van Huben ,  Jie Zheng

IPC: G06F3/06 ,  G11C7/10

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

公开(公告)号：US20190163378A1

公开(公告)日：2019-05-30

申请号：US15825882

申请日：2017-11-29

Applicant: International Business Machines Corporation

Inventor： Steven R. Carlough ,  Susan M. Eickhoff ,  Patrick J. Meaney ,  Stephen J. Powell ,  Gary A. Van Huben ,  Jie Zheng

IPC: G06F3/06 ,  G06F12/06

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.

公开(公告)号：US20180329777A1

公开(公告)日：2018-11-15

申请号：US16043362

申请日：2018-07-24

Applicant: International Business Machines Corporation

Inventor： Glenn D. Gilda ,  Patrick J. Meaney

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/44

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C29/44 ,  G11C29/52

Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.

公开(公告)号：US20180173429A1

公开(公告)日：2018-06-21

申请号：US15659863

申请日：2017-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James J. Bonanno ,  Michael J. Cadigan, JR. ,  Adam B. Collura ,  Daniel Lipetz ,  Patrick J. Meaney ,  Craig R. Walters

IPC: G06F3/06 ,  G11C11/4091 ,  G11C11/406

CPC classification number: G06F3/0611 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/16 ,  G11C5/04 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227

Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

公开(公告)号：US09645904B2

公开(公告)日：2017-05-09

申请号：US15247239

申请日：2016-08-25

Applicant: International Business Machines Corporation

Inventor： Michael F. Fee ,  Patrick J. Meaney ,  Arthur J. O'Neill, Jr.

IPC: G06F11/07 ,  G06F11/10 ,  G06F11/20 ,  G11C29/00 ,  G06F3/06 ,  G11C29/42 ,  G11C29/52 ,  G11C29/56 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  H03M13/19 ,  G11C29/24 ,  G11C15/00 ,  G11C29/04

CPC classification number: G06F11/2094 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0673 ,  G06F3/0679 ,  G06F11/07 ,  G06F11/0727 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0763 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1024 ,  G06F11/1028 ,  G06F11/1048 ,  G06F11/106 ,  G06F11/1064 ,  G06F11/20 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2201/85 ,  G06F2212/1032 ,  G11C15/00 ,  G11C29/00 ,  G11C29/24 ,  G11C29/42 ,  G11C29/52 ,  G11C29/56008 ,  G11C29/76 ,  G11C2029/0411 ,  H03M13/19

Abstract: A technique is provided for accumulating failures. A failure of a first row is detected in a group of array macros, the first row having first row address values. A mask has mask bits corresponding to each of the first row address values. The mask bits are initially in active status. A failure of a second row, having second row address values, is detected. When none of the first row address values matches the second row address values, and when mask bits are all in the active status, the array macros are determined to be bad. When at least one of the first row address values matches the second row address values, mask bits that correspond to at least one of the first row address values that match are kept in active status, and mask bits that correspond to non-matching first address values are set to inactive status.

公开(公告)号：US09594646B2

公开(公告)日：2017-03-14

申请号：US15252435

申请日：2016-08-31

Applicant: International Business Machines Corporation

Inventor： Glenn D. Gilda ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  John S. Dodson

IPC: G06F1/12 ,  G06F11/16 ,  G06F3/06 ,  G06F13/16 ,  G06F1/04 ,  G06F1/10

CPC classification number: G06F11/1662 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/0757 ,  G06F11/1044 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2007 ,  G06F13/1673

Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a computer implemented method that includes receiving an out-of-synchronization indication associated with at least one of a plurality of channels in the memory system. A memory control unit in communication with the channels performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.

Abstract translation: 实施例涉及重新建立在存储器系统中的多个通道之间的同步。 一个方面是计算机实现的方法，其包括接收与存储器系统中的多个信道中的至少一个相关联的失步指示。 与信道通信的存储器控​​制单元执行重新建立同步的第一阶段，其包括选择性地停止多个信道上的新业务，等待第一时间段到期，基于第一时间段在多个信道上恢复业务 到期并验证在第二时间段内重新建立同步。

公开(公告)号：US20160357650A1

公开(公告)日：2016-12-08

申请号：US15247239

申请日：2016-08-25

Applicant: International Business Machines Corporation

Inventor： Michael F. Fee ,  Patrick J. Meaney ,  Arthur J. O'Neill, JR.

IPC: G06F11/20 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/0842 ,  H03M13/19 ,  G06F11/10 ,  G06F12/084

CPC classification number: G06F11/2094 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0673 ,  G06F3/0679 ,  G06F11/07 ,  G06F11/0727 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0763 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1024 ,  G06F11/1028 ,  G06F11/1048 ,  G06F11/106 ,  G06F11/1064 ,  G06F11/20 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2201/85 ,  G06F2212/1032 ,  G11C15/00 ,  G11C29/00 ,  G11C29/24 ,  G11C29/42 ,  G11C29/52 ,  G11C29/56008 ,  G11C29/76 ,  G11C2029/0411 ,  H03M13/19

Abstract: A technique is provided for accumulating failures. A failure of a first row is detected in a group of array macros, the first row having first row address values. A mask has mask bits corresponding to each of the first row address values. The mask bits are initially in active status. A failure of a second row, having second row address values, is detected. When none of the first row address values matches the second row address values, and when mask bits are all in the active status, the array macros are determined to be bad. When at least one of the first row address values matches the second row address values, mask bits that correspond to at least one of the first row address values that match are kept in active status, and mask bits that correspond to non-matching first address values are set to inactive status.