公开(公告)号：US20060091489A1

公开(公告)日：2006-05-04

申请号：US10904255

申请日：2004-11-01

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L21/336

CPC分类号： H01L31/105 ,  H01L31/03529 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： Trench type PIN photodetectors are formed by etching two sets of trenches simultaneously in a semiconductor substrate, the wide trenches having a width more than twice as great as the narrow trenches by a process margin; conformally filling both types of trenches with a sacrificial material doped with a first dopant and having a first thickness slightly greater than one half the width of the narrow trenches, so that the wide trenches have a remaining central aperture; stripping the sacrificial material from the wide trenches in an etch that removes a first thickness, thereby emptying the wide trenches; a) filling the wide trenches with a second sacrificial material of opposite polarity; or b) doping the wide trenches from the ambient such as by gas phase doping, plasma doping, ion implantation, liquid phase doping, infusion doping and plasma immersion ion implantation; diffusing the dopants into the substrate, forming p and n regions of the PIN diode; removing the first and the second sacrificial materials, and filling both the wide and the narrow sets of trenches with the same conductive material in contact with the diffused p and n regions.

摘要翻译： 通过在半导体衬底中同时蚀刻两组沟槽形成沟槽型PIN光电检测器，宽沟槽的宽度是窄沟槽的两倍以上的加工余量; 用掺杂有第一掺杂剂的牺牲材料保形地填充两种类型的沟槽，并且具有略大于窄沟槽宽度的一半的第一厚度，使得宽沟槽具有剩余的中心孔径; 在去除第一厚度的蚀刻中从宽的沟槽剥离牺牲材料，从而排空宽的沟槽; a）用相反极性的第二牺牲材料填充宽的沟槽; 或b）通过气相掺杂，等离子体掺杂，离子注入，液相掺杂，浸渍掺杂和等离子体浸入离子注入等方式，从环境中掺杂宽沟槽; 将掺杂剂扩散到衬底中，形成PIN二极管的p区和n区; 去除第一和第二牺牲材料，并用与扩散的p和n区域接触的相同导电材料填充宽和窄的沟槽组。

公开(公告)号：US20050164447A1

公开(公告)日：2005-07-28

申请号：US11085663

申请日：2005-03-21

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  C. Sung

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  C. Sung

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02

CPC分类号： H01L27/10876 ,  H01L27/0207 ,  H01L27/10864 ,  H01L27/1087 ,  H01L29/945

摘要： A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, and the dopant source material is annealed so as to form a buried plate of a trench capacitor. The buried plate is self aligned to the shaped upper portion of the trench.

公开(公告)号：US09515140B2

公开(公告)日：2016-12-06

申请号：US12015272

申请日：2008-01-16

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L29/73 ,  H01L29/10 ,  H01L29/739 ,  H01L29/786 ,  H01L21/8234

CPC分类号： H01L29/1054 ,  H01L21/823412 ,  H01L29/739 ,  H01L29/78687

摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

摘要翻译： 一种包括在基板上形成应变材料和松弛材料的图案的方法; 在应变材料中形成应变装置; 并且公开了在松弛材料中形成非应变装置。 在一个实施例中，应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是处于正常状态的Si。 在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，其晶格常数/结构与衬底失配。 在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。 在另一个实施例中，使用掺碳硅或锗掺杂硅来形成应变材料。 该结构包括具有图案化的应变和非应变材料的多层基底。

公开(公告)号：US08703552B2

公开(公告)日：2014-04-22

申请号：US13419624

申请日：2012-03-14

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L27/06 ,  H01L21/8242

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181

摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.

摘要翻译： 提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。 在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。 沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。 第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。 第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。 在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。 还提供了一种用于形成上述装置的方法。

公开(公告)号：US08236634B1

公开(公告)日：2012-08-07

申请号：US13050023

申请日：2011-03-17

申请人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L27/088

CPC分类号： H01L27/1211 ,  H01L21/845

摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.

摘要翻译： 薄半导体区域和厚半导体区域被形成为绝缘体层。 厚半导体区域包括至少一个半导体鳍片。 图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。 半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。 在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。 此外，翅片源极和漏极区域在薄的鳍部上生长。 源极和漏极区域，鳍片和一次性栅电极被平坦化。 一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

公开(公告)号：US20120171821A1

公开(公告)日：2012-07-05

申请号：US13419624

申请日：2012-03-14

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L21/786

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181

摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.

摘要翻译： 提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。 在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。 沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。 第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。 第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。 在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。 还提供了一种用于形成上述装置的方法。

公开(公告)号：US07919347B2

公开(公告)日：2011-04-05

申请号：US12349018

申请日：2009-01-06

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl John Radens ,  William Robert Tonti

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl John Radens ,  William Robert Tonti

IPC分类号： H01L29/868

CPC分类号： H01L29/868 ,  H01L29/6609

摘要： Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.

摘要翻译： 制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构。 一种方法包括：在硅衬底中形成沟槽; 在所述衬底中形成邻接所述沟槽的掺杂区域; 在沟槽的表面上生长本征的外延硅层; 沉积掺杂多晶硅层以填充沟槽中的剩余空间，执行化学机械抛光，使得本征外延硅层和掺杂多晶硅层的顶表面是共面的; 在衬底中形成绝缘隔离层; 在隔离层的顶部形成介电层; 以及通过介电层形成第一金属接触到掺杂多晶硅层，以及通过第二接触到掺杂区域介电层并通过隔离层。

公开(公告)号：US07821098B2

公开(公告)日：2010-10-26

申请号：US12103000

申请日：2008-04-15

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L29/93

CPC分类号： H01L29/945 ,  H01L29/66181

摘要： A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. The method further comprises the steps of removing portions of the blocking layer on the {110} side wall surfaces without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.

摘要翻译： 半导体结构。 半导体结构包括半导体衬底，半导体衬底中的沟槽。 沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。 半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。 该方法还包括以下步骤：除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围 周围。

公开(公告)号：US07790530B2

公开(公告)日：2010-09-07

申请号：US12254960

申请日：2008-10-21

申请人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

发明人： Jack A. Mandelman ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Geng Wang

IPC分类号： H01L21/00

CPC分类号： H01L27/108 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1203

摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

公开(公告)号：US07732872B2

公开(公告)日：2010-06-08

申请号：US11924053

申请日：2007-10-25

申请人： Kangguo Cheng ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

发明人： Kangguo Cheng ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L27/088

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.

摘要翻译： 在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。 在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整 氧化层。 还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。 在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。