公开(公告)号：US07206216B2

公开(公告)日：2007-04-17

申请号：US11057682

申请日：2005-02-15

申请人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

发明人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3454 ,  G11C2013/0092 ,  G11C2213/82

摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

公开(公告)号：US20050185445A1

公开(公告)日：2005-08-25

申请号：US11057682

申请日：2005-02-15

申请人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

发明人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

IPC分类号： G11C13/00 ,  G06F13/00 ,  G11C11/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C19/08 ,  H01L27/10 ,  H01L27/105

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3454 ,  G11C2013/0092 ,  G11C2213/82

摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

公开(公告)号：US06862227B2

公开(公告)日：2005-03-01

申请号：US10445919

申请日：2003-05-28

申请人： Masanao Yamaoka ,  Kenichi Osada

发明人： Masanao Yamaoka ,  Kenichi Osada

IPC分类号： G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C11/4193 ,  G11C29/02 ,  G11C11/41

CPC分类号： G11C29/02 ,  G11C5/146 ,  G11C5/147 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

摘要： An SRAM circuit which can be operated at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.

摘要翻译： 一种SRAM电路，通过增加或优化SRAM电路的工作裕度，可以以较低的工作电压工作，特别是在低工作电压下工作。 检测SRAM电路中产生的晶体管的阈值电压，以将存储单元的工作电压与外围电路的工作电压进行比较，以将其调整到最佳值，并进一步控制衬底偏置电压。

公开(公告)号：US06839268B2

公开(公告)日：2005-01-04

申请号：US10686569

申请日：2003-10-17

申请人： Kenichi Osada ,  Hisayuki Higuchi ,  Koichiro Ishibashi

发明人： Kenichi Osada ,  Hisayuki Higuchi ,  Koichiro Ishibashi

IPC分类号： G11C11/413 ,  G06F12/08 ,  G11C7/06 ,  G11C7/18 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC分类号： G11C7/18 ,  G06F12/0802 ,  G11C7/065

摘要： A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

公开(公告)号：US06756814B2

公开(公告)日：2004-06-29

申请号：US10345242

申请日：2003-01-16

申请人： Yoshikazu Saitou ,  Kenichi Osada

发明人： Yoshikazu Saitou ,  Kenichi Osada

IPC分类号： H03K19175

CPC分类号： H03K19/0016

摘要： The present invention is directed to simplify a circuit for fixing an output logic of a logic gate while suppressing a subthreshold current. A logic circuit has an n-channel type first transistor capable of interrupting power supply to a logic gate in accordance with an input control signal, and a p-channel type second transistor capable of fixing an output node of the logic gate to a high level interlockingly with the power supply interrupting operation by the first transistor, and a threshold of the first transistor is set to be higher than that of a transistor as a component of the logic gate. Means for interrupting the power supply to the logic gate is realized by the first transistor, and means for fixing an output node of the logic gate to the high level is realized by the second transistor, thereby simplifying the circuit for fixing the output logic of the logic gate while suppressing a subthreshold current.

摘要翻译： 本发明旨在简化用于在抑制亚阈值电流的同时固定逻辑门的输出逻辑的电路。 逻辑电路具有能够根据输入控制信号中断到逻辑门的电源的n沟道型第一晶体管，以及能够将逻辑门的输出节点固定为高电平的p沟道型第二晶体管 与第一晶体管的电源中断操作互锁，并且将第一晶体管的阈值设置为高于作为逻辑门的组件的晶体管的阈值。 用于中断对逻辑门的电源的装置由第一晶体管实现，并且通过第二晶体管实现将逻辑门的输出节点固定为高电平的装置，从而简化用于固定逻辑门的输出逻辑的电路 同时抑制亚阈值电流。

公开(公告)号：US06657911B2

公开(公告)日：2003-12-02

申请号：US10274985

申请日：2002-10-22

申请人： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

发明人： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC分类号： G11C700

CPC分类号： G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

摘要： The present invention relates to a system LSI consolidating a logic circuit and an SRAM circuit. More specifically, the present invention relates to a semiconductor device which can reduce a leakage current and the power consumption in the standby state. The logic circuit in the system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing a leakage current. At the same time, the SRAM circuit controls a substrate bias to reduce the leakage current.

摘要翻译： 本发明涉及一种整合逻辑电路和SRAM电路的系统LSI。 更具体地说，本发明涉及能够减少待机状态下的漏电流和功耗的半导体装置。系统LSI中的逻辑电路设置有电源开关，以便在断开时切断开关 待机，减少漏电流。 同时，SRAM电路控制衬底偏置以减少漏电流。

公开(公告)号：US06559006B2

公开(公告)日：2003-05-06

申请号：US10157978

申请日：2002-05-31

申请人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

发明人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

IPC分类号： H01L218242

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质 介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

公开(公告)号：US06525985B2

公开(公告)日：2003-02-25

申请号：US09577366

申请日：2000-05-23

申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

IPC分类号： G11C514

CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02D10/13

摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

公开(公告)号：US06515894B2

公开(公告)日：2003-02-04

申请号：US09988197

申请日：2001-11-19

申请人： Kenichi Osada ,  Hisayuki Higuchi ,  Koichiro Ishibashi

发明人： Kenichi Osada ,  Hisayuki Higuchi ,  Koichiro Ishibashi

IPC分类号： G11C1100

CPC分类号： G11C7/18 ,  G06F12/0802 ,  G11C7/065

摘要： A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

公开(公告)号：US06436753B1

公开(公告)日：2002-08-20

申请号：US09372007

申请日：1999-08-11

申请人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

发明人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

IPC分类号： H01L218244

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits, such as a microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，对于形成SRAM的存储单元的负载电阻QL的转移MISFET Qt和MISFET相对有意地高于诸如微处理器的SRAM外围电路和逻辑电路的预定MISFET的Vth， 引入杂质引入步骤，用于设置用于设置预定MISFET的Vth的杂质引入步骤的驱动MISFET Qd，负载电阻的转移MISFET Qt和MISFET的Vth。