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100 条记录 (耗时 0.033 秒)

    Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit
    62.
    发明授权
    Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit 有权
    非易失性逻辑电路，包括非易失性逻辑电路的集成电路和操作集成电路的方法

    公开(公告)号：US08509004B2

    公开(公告)日：2013-08-13

    申请号：US12801502

    申请日：2010-06-11

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Kwang-seok Kim ,  Kee-won Kim

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Kwang-seok Kim ,  Kee-won Kim

    IPC分类号： G11C7/10

    CPC分类号： H03K19/1733 ,  G11C14/0054 ,  G11C14/0081 ,  G11C14/009 ,  H03K3/356008

    摘要： A nonvolatile logic circuit includes a latch unit including a pair of first and second latch nodes; and a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively. A write operation is performed on the first and second nonvolatile memory cells according to a direction of a current flowing through the first and second nonvolatile memory cells when a write enable signal is activated. The direction of flow of current determined based on data on the respective first and second latch nodes, and a logic value written on the first nonvolatile memory cells is different from a logic value written on the second nonvolatile memory cell.

    摘要翻译： 非易失性逻辑电路包括：锁存单元，包括一对第一和第二锁存节点; 以及分别电连接到第一和第二锁存节点的一对第一和第二非易失性存储单元。 当写入使能信号被激活时，根据流过第一和第二非易失性存储器单元的电流的方向在第一和第二非易失性存储器单元上执行写入操作。 基于相应的第一和第二锁存节点上的数据确定的电流的流动方向和写在第一非易失性存储器单元上的逻辑值与写入第二非易失性存储单元的逻辑值不同。

    Nonvolatile memory devices and methods of operating the same
    65.
    发明授权
    Nonvolatile memory devices and methods of operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US07948019B2

    公开(公告)日：2011-05-24

    申请号：US12071451

    申请日：2008-02-21

    申请人： Young-gu Jin ,  Ki-ha Hong ,  Yoon-dong Park ,  Jai-kwang Shin ,  Suk-pil Kim

    发明人： Young-gu Jin ,  Ki-ha Hong ,  Yoon-dong Park ,  Jai-kwang Shin ,  Suk-pil Kim

    IPC分类号： H01L29/788

    CPC分类号： G11C16/0416 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/0673 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    摘要： Example embodiments include nonvolatile memory devices that have good operation performance and may be made in a highly integrated structure, and methods of operating the same. Example embodiments of the nonvolatile memory devices include a substrate electrode, and a semiconductor channel layer on the substrate electrode, a floating gate electrode on the substrate electrode, wherein a portion of the floating gate electrode faces the semiconductor channel layer, a control gate electrode on the floating gate electrode, and wherein a distance between a portion of the floating gate electrode and the substrate electrode is smaller than a distance between the semiconductor channel layer and the substrate electrode wherein charge tunneling occurs.

    摘要翻译： 示例性实施例包括具有良好操作性能并且可以以高度集成的结构制造的非易失性存储器件及其操作方法。 非易失性存储器件的示例性实施例包括衬底电极和衬底电极上的半导体沟道层，衬底电极上的浮置栅电极，其中浮置栅电极的一部分面向半导体沟道层，控制栅极电极 所述浮置栅极电极，并且其中所述浮置栅电极的一部分与所述基板电极之间的距离小于半导体沟道层与发生电荷隧道的基板电极之间的距离。

    Image sensors and methods of operating the same
    66.
    发明申请
    Image sensors and methods of operating the same 有权
    图像传感器及其操作方法

    公开(公告)号：US20110108704A1

    公开(公告)日：2011-05-12

    申请号：US12805723

    申请日：2010-08-17

    申请人： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin ,  Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Sang-hun Jeon

    发明人： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin ,  Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Sang-hun Jeon

    IPC分类号： H01L27/146 ,  H01L31/09 ,  H01L31/101 ,  H01L31/102

    CPC分类号： H04N9/045 ,  H01L27/14643 ,  H04N5/3745

    摘要： Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively.

    摘要翻译： 图像传感器及其操作方法。 图像传感器包括包括多个像素的像素阵列。 多个像素中的每一个包括光电传感器，其电压 - 电流特性根据入射光的能量而变化，并且产生由入射光的能量确定的感测电流; 根据用于复位所述多个像素中的至少一个的复位信号，被激活以产生参考电流的复位单元; 以及转换单元，其将感测电流和参考电流分别转换为感测电压和参考电压。

    Ferroelectric memory devices and operating methods thereof
    67.
    发明申请
    Ferroelectric memory devices and operating methods thereof 有权
    铁电存储器件及其操作方法

    公开(公告)号：US20110075467A1

    公开(公告)日：2011-03-31

    申请号：US12923131

    申请日：2010-09-03

    申请人： Ki-ha Hong ,  Jeong-seob Kim ,  Jai-kwang Shin

    发明人： Ki-ha Hong ,  Jeong-seob Kim ,  Jai-kwang Shin

    IPC分类号： G11C11/22 ,  H01L29/82 ,  G11C7/00

    CPC分类号： G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/11597 ,  H01L27/1203 ,  H01L29/1606 ,  H01L29/78391

    摘要： A ferroelectric memory device having a NAND array of a plurality of ferroelectric memory cells includes: a fully depleted channel layer; a gate electrode layer; and a ferroelectric layer located between the channel layer and the gate electrode layer. The data of the plurality of ferroelectric memory cells is erased by applying a first erase voltage to a bit line and a common source line and applying a second erase voltage to a string selection line and a ground selection line.

    摘要翻译： 具有多个铁电存储单元的NAND阵列的铁电存储器件包括：完全耗尽的沟道层; 栅电极层; 以及位于沟道层和栅电极层之间的铁电层。 通过对位线和公共源极线施加第一擦除电压并向串选择线和地选择线施加第二擦除电压来擦除多个铁电存储单元的数据。

    Semiconductor device and method of operating the semiconductor device
    70.
    发明授权
    Semiconductor device and method of operating the semiconductor device 有权
    半导体器件及半导体器件的操作方法

    公开(公告)号：US08638163B2

    公开(公告)日：2014-01-28

    申请号：US13550848

    申请日：2012-07-17

    申请人： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin

    发明人： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin

    IPC分类号： G05F1/10

    CPC分类号： H01L29/78684 ,  G11C29/12005

    摘要： A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage.

    摘要翻译： 一种半导体器件和操作半导体器件的方法。 半导体器件包括被配置为产生测试电压的电压发生器，被配置为基于测试电压接收栅极 - 源极电压的石墨烯晶体管，以及检测器，被配置为检测栅极 - 源极电压是否为石墨烯的狄拉克电压 并输出施加到电压发生器的反馈信号，指示栅极 - 源极电压是否为狄拉克电压。