公开(公告)号：US06930036B2

公开(公告)日：2005-08-16

申请号：US10695159

申请日：2003-10-28

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/76835 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76832 ,  H01L2221/1036

摘要： A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.

摘要翻译： 在半导体器件中制造多电平互连结构的方法包括在第一层Cu层上连续形成抗扩散膜和层间电介质膜的步骤，在层间绝缘膜上形成第一至第三硬掩模膜， 通过使用第一硬掩模来形成第一硬掩模以蚀刻层间电介质膜，通过使用第三硬掩模膜来蚀刻第一和第二硬掩模膜和层间绝缘膜的顶部以形成沟槽， 扩散膜形成通孔。 第一硬掩模膜在去除第二和第三硬掩模膜期间保护层间电介质膜。

公开(公告)号：US06670709B2

公开(公告)日：2003-12-30

申请号：US09779584

申请日：2001-02-09

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L23485

CPC分类号： H01L21/76829 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76825 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first HSQ film composed of a Si—O-based film with a low dielectric constant is formed on a first wiring via a protective insulation film, and the surface of this first HSQ film is reformed to form a first SRO layer. Then, a second HSQ film is formed on this first SRO layer, and the surface of the second HSQ film is reformed to form a second SRO layer. Next, a via-hole is formed within a predetermined region, which reaches the protective insulation film on the first wiring. Then, wiring trenches forming a second wiring are formed within predetermined regions of the second HSQ film and the second SRO film while using the first SRO film as an etching stopper film. Thereafter, the protective insulation film at the bottom of the via-hole is etched and removed, and the wiring trenches and the via-hole are embedded with a conductive film. Then, the conductive film on the second SRO layer is removed while using the second SRO layer as a CMP stopper film.

摘要翻译： 通过保护绝缘膜在第一布线上形成由具有低介电常数的Si-O基膜构成的第一HSQ膜，并将该第一HSQ膜的表面重整形成第一SRO层。 然后，在该第一SRO层上形成第二HSQ膜，将第二HSQ膜的表面重新形成第二SRO层。 接下来，在到达第一布线上的保护绝缘膜的预定区域内形成通孔。 然后，在使用第一SRO膜作为蚀刻停止膜的同时，在第二HSQ膜和第二SRO膜的预定区域内形成形成第二布线的布线沟槽。 此后，蚀刻去除通孔底部的保护绝缘膜，并且布线沟槽和通孔嵌入导电膜。 然后，在使用第二SRO层作为CMP阻挡膜的同时去除第二SRO层上的导电膜。

公开(公告)号：US06514852B2

公开(公告)日：2003-02-04

申请号：US09910994

申请日：2001-07-23

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76832 ,  H01L2221/1036

摘要： A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.

公开(公告)号：US06383927B2

公开(公告)日：2002-05-07

申请号：US09513926

申请日：2000-02-28

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L2144

CPC分类号： H01L21/28194 ,  H01L21/02134 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02282 ,  H01L21/28211 ,  H01L21/31058 ,  H01L21/3124 ,  H01L21/31662 ,  H01L21/324 ,  Y10S438/913

摘要： Semiconductor wafers on a boat are inserted into a furnace chamber of a vertical oxidation/diffusion furnace, and helium gas and argon gas are injected into the furnace chamber during the insertion of the boat, so that the light helium gas fills the furnace chamber without residual air and the heavy argon gas pushes out the residual air from gaps between the semiconductor wafers.

摘要翻译： 将船上的半导体晶片插入垂直氧化/扩散炉的炉室中，并且在船的插入期间将氦气和氩气注入炉室中，使得轻氦气填充炉室而不残留 空气和重氩气从半导体晶片之间的间隙推出剩余空气。

公开(公告)号：US06294833B1

公开(公告)日：2001-09-25

申请号：US09481885

申请日：2000-01-12

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L2348

CPC分类号： H01L21/76802 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834

摘要： Described in the present invention is a semiconductor device in which a plurality of interconnect lines are disposed, through an insulating layer, on the same layer above a semiconductor substrate having a semiconductor element; a first interlevel insulator is formed selectively in a narrowly-spaced region between adjacent interconnect lines; a second interlevel insulator is formed in a widely-spaced region between said adjacent interconnect lines, and the first interlevel insulator has a smaller dielectric constant than the second interlevel insulator. According to such a constitution, strength and reliability can be heightened and performance can be improved easily even in a miniaturized interconnect structure.

公开(公告)号：US5939771A

公开(公告)日：1999-08-17

申请号：US739746

申请日：1996-10-29

申请人： Tatsuya Usami ,  Tetsuya Homma

发明人： Tatsuya Usami ,  Tetsuya Homma

IPC分类号： H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044

摘要： On manufacturing a semiconductor device, preparation is made of an organic layer (101) of a resin which has a relative dielectric constant between 1.8 and 3.5, both inclusive, and which is selected from the group consisting of a polyimide resin and a fluororesin. The organic layer has a slit. A first metal (105) is buried in the slit. A silicon oxide layer (106) containing fluorine is formed on the organic layer so that the silicon oxide layer has a hole on the first metal. A second metal (107) is buried in the hole. Preferably, an additional organic layer (101') of the resin is formed on the silicon oxide layer so that the additional organic layer has an additional slit on the second metal. In this case, a first additional metal (105') is buried in the additional slit. In addition, an additional silicon oxide layer (106') containing fluorine may be formed on the additional organic layer so that the additional silicon oxide layer has an additional hole on the first additional metal. In this event, a second additional metal (107') is buried in the additional hole.

摘要翻译： 在制造半导体器件时，由相对介电常数在1.8和3.5之间的树脂的有机层（101）制成，并且选自聚酰亚胺树脂和氟树脂。 有机层具有狭缝。 第一金属（105）被埋在狭缝中。 在有机层上形成含有氟的氧化硅层（106），使得氧化硅层在第一金属上具有孔。 第二金属（107）被埋在孔中。 优选地，在氧化硅层上形成树脂的附加有机层（101'），使得附加的有机层在第二金属上具有附加的狭缝。 在这种情况下，第一附加金属（105'）埋在附加狭缝中。 此外，可以在附加的有机层上形成含有氟的另外的氧化硅层（106'），使得另外的氧化硅层在第一附加金属上具有另外的孔。 在这种情况下，第二附加金属（107'）埋在附加孔中。

公开(公告)号：US5751050A

公开(公告)日：1998-05-12

申请号：US736506

申请日：1996-10-24

申请人： Hiraku Ishikawa ,  Tatsuya Usami

发明人： Hiraku Ishikawa ,  Tatsuya Usami

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L27/06 ,  H01L31/0368

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0688

摘要： A base insulator film comprised of a silicon oxide film or the like is formed on the surface of a silicon substrate, and a non-doped polysilicon film (resistor layer) is selectively formed on the base insulator film by thermal CVD. A first silicon oxide film and a BPSG film are sequentially formed on the entire surfaces of the base insulator film and the polysilicon film. Then, two openings which reach the polysilicon film are formed in the BPSG film and the first silicon oxide film, and an impurity is selectively doped into the surface of the polysilicon film through those openings. As a result, a high-resistance section is formed in the polysilicon film between the two openings. Then, the openings are filled with metal layers, and then metal wires to be connected to the metal layers are formed on the surface of the BPSG film. Then, a second silicon oxide film is formed on the entire surfaces of the BPSG film and the metal wires by bias ECR (Electron Cyclotron Resonance)--CVD having a high electric field to coat the metal wires and the like. The high electric field ECR-CVD deposition increases the hydrogen atomic concentration of the polysilicon resistor layer so as to stabilize the resistance against diffusion of lower atomic concentrations of incidental hydrogen atoms from various other interlayer insulating layers.

摘要翻译： 在硅衬底的表面上形成由氧化硅膜等构成的基底绝缘膜，通过热CVD在基底绝缘膜上选择性地形成非掺杂多晶硅膜（电阻层）。 在基底绝缘体膜和多晶硅膜的整个表面上依次形成第一氧化硅膜和BPSG膜。 然后，在BPSG膜和第一氧化硅膜中形成到达多晶硅膜的两个开口，并且通过这些开口将杂质选择性地掺杂到多晶硅膜的表面中。 结果，在两个开口之间的多晶硅膜中形成高电阻部分。 然后，用金属层填充开口，然后在BPSG膜的表面上形成要连接到金属层的金属线。 然后，通过具有高电场的偏置ECR（电子回旋共振）-CVD，在BPSG膜和金属线的整个表面上形成第二氧化硅膜以涂覆金属线等。 高电场ECR-CVD沉积增加了多晶硅电阻层的氢原子浓度，以稳定来自各种其它层间绝缘层的较低原子浓度的附带氢原子的扩散阻力。

公开(公告)号：US5503678A

公开(公告)日：1996-04-02

申请号：US334303

申请日：1994-11-04

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L21/205 ,  C23C16/44 ,  C23C16/455 ,  H01L21/31 ,  C23C16/00

CPC分类号： C23C16/4558 ,  C23C16/45589

摘要： A vertical low pressure CVD (Chemical Vapor Deposition) apparatus includes a first and a second annular nozzle assigned to silane gas and an oxidizing gas, respectively. The first nozzle adjoins the lowermost portion of a boat loaded with a stack of wafers. The two nozzles are spaced from each other and have a plurality of holes arranged in a similar fashion. The oxidizing gas, jetted from the second nozzle, reaches the first nozzle over the same distance and, therefore, in the same amount as measured around the first nozzle. As a result, the two kinds of gas are mixed in a uniform ratio. The distance between the two nozzles may be changed for different types of oxidizing gases to uniformly mix the oxidizing gas with the silane gas without an early reaction.

摘要翻译： 垂直低压CVD（化学气相沉积）装置分别包括分配给硅烷气体和氧化气体的第一和第二环形喷嘴。 第一喷嘴邻接装载有一叠晶片的船的最下部分。 两个喷嘴彼此间隔开并且具有以类似方式布置的多个孔。 从第二喷嘴喷射的氧化气体以相同的距离到达第一喷嘴，因此与第一喷嘴周围测量的量相同。 结果，两种气体以均匀的比例混合。 对于不同类型的氧化气体，可以改变两个喷嘴之间的距离，以使氧化气体与硅烷气体均匀混合而不会发生早期反应。

公开(公告)号：US08722532B2

公开(公告)日：2014-05-13

申请号：US13567546

申请日：2012-08-06

申请人： Tatsuya Usami ,  Hiroshi Kitajima

发明人： Tatsuya Usami ,  Hiroshi Kitajima

IPC分类号： H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/32139 ,  H01L21/7685 ,  H01L21/76897 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first wiring is disposed over a semiconductor substrate. A first via is disposed over the first wiring. Further, the bottom surface of the first via is in contact with the first wiring. A first insulation layer is disposed over the semiconductor substrate, and is in contact with at least the top surface of the first wiring and the side surface of the first via. At least a part of each side surface of the first wiring and the first via cuts off each metal crystal grain.

摘要翻译： 第一布线设置在半导体衬底上。 第一通孔布置在第一布线上。 此外，第一通孔的底面与第一布线接触。 第一绝缘层设置在半导体衬底上，并且至少与第一布线的顶表面和第一通孔的侧表面接触。 第一布线和第一通孔的每个侧表面的至少一部分切断每个金属晶粒。

公开(公告)号：US08624399B2

公开(公告)日：2014-01-07

申请号：US12662331

申请日：2010-04-12

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L23/48

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. A second insulating layer is formed at least over the first insulating layer and the air gap. The second insulating layer does not cover the interconnect. An etching stopper film is formed at least over the second insulating layer. The etching stopper film is formed over the second insulating layer and the interconnect. A third insulating layer is formed over the etching stopper film. A via is provided in the third insulating layer so as to be connected to the interconnect.

摘要翻译： 在第一绝缘层中提供互连，并且互连的上表面高于第一绝缘层的上表面。 在互连和第一绝缘层之间设置气隙。 至少在第一绝缘层和气隙上形成第二绝缘层。 第二绝缘层不覆盖互连。 至少在第二绝缘层上形成蚀刻停止膜。 蚀刻阻挡膜形成在第二绝缘层和互连之上。 在蚀刻停止膜上形成第三绝缘层。 通孔设置在第三绝缘层中以连接到互连。