利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

81 条记录 (耗时 0.031 秒)

    Method and system for DC-balancing at the physical layer
    61.
    发明授权
    Method and system for DC-balancing at the physical layer 有权
    物理层直流平衡的方法和系统

    公开(公告)号：US06771192B1

    公开(公告)日：2004-08-03

    申请号：US10045600

    申请日：2001-11-07

    申请人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

    发明人： Dongyun Lee ,  Yeshik Shin ,  David D. Lee ,  Deog-Kyoon Jeong ,  Shing Kong

    IPC分类号： H03M500

    CPC分类号： H04L47/10 ,  H04L47/245 ,  H04L47/34 ,  H04L47/365

    摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

    摘要翻译： 用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。 存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。 存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的 。 存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

    CMOS driver and on-chip termination for gigabaud speed data communication
    62.
    发明授权
    CMOS driver and on-chip termination for gigabaud speed data communication 有权
    CMOS驱动器和片上终端，用于千兆位速度数据通信

    公开(公告)号：US06560290B2

    公开(公告)日：2003-05-06

    申请号：US09234619

    申请日：1999-01-20

    申请人： Gijung Ahn ,  Deog-Kyoon Jeong ,  Gyudong Kim

    发明人： Gijung Ahn ,  Deog-Kyoon Jeong ,  Gyudong Kim

    IPC分类号： H04L2700

    CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0292

    摘要： New very high-speed CMOS techniques are used to achieve a CMOS driver operating at gigabaud speeds. Such a driver may be manufactured more easily than drivers that use GaAs or bipolar techniques and further may be easily integrated with other CMOS circuits. A communication system utilizing the gigabaud CMOS driver may additionally include a receiver with on-chip termination to significantly reduce distortion in the presence of parasitic capacitance in inductance in comparison to a receiver with external termination. Furthermore, the communication system may include a phase tracker and a frame aligner. The phase tracker continously monitors the most frequent transition edges in the oversampled data so that the phase of the receiver clock keeps track of the sender clock. The frame aligner comprises a comma detector which enables instant synchronization of data words with a single comma character within a serial data stream.

    摘要翻译： 使用新的非常高速的CMOS技术来实现以千兆位速度运行的CMOS驱动器。 这样的驱动器可以比使用GaAs或双极技术的驱动器更容易制造，并且还可以容易地与其他CMOS电路集成。 与具有外部端接的接收机相比，使用千兆位CMOS驱动器的通信系统可以另外包括具有片上终止的接收器，以在存在电感中的寄生电容的情况下显着减少失真。 此外，通信系统可以包括相位跟踪器和帧对准器。 相位跟踪器连续监视过采样数据中最频繁的转换边沿，使得接收机时钟的相位跟踪发送器时钟。 帧对准器包括逗号检测器，该逗号检测器使串行数据流中具有单个逗号字符的数据字能够即时同步。

    System for Distributing Clocks
    63.
    发明授权
    System for Distributing Clocks 失效
    分配时钟系统

    公开(公告)号：US06211714B1

    公开(公告)日：2001-04-03

    申请号：US09013679

    申请日：1998-01-26

    申请人： Deog-Kyoon Jeong

    发明人： Deog-Kyoon Jeong

    IPC分类号： G06F104

    CPC分类号： H04L7/0338 ,  H03K19/018592 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/0996 ,  H03M9/00 ,  H04J3/047 ,  H04L5/1423 ,  H04L7/0008 ,  H04L7/0337 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/085

    摘要： A system for converting between parallel data and serial data is described. In the system, individual bits of the parallel data are latched into individual registers. Each register is coupled to a corresponding AND gate which is also connected to receive phased clock signals. The output terminals of the AND gates are connected to an OR gate. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

    摘要翻译： 描述用于在并行数据和串行数据之间转换的系统。 在系统中，并行数据的各个位被锁存到各个寄存器中。 每个寄存器耦合到相应的与门，该门也被连接以接收相位时钟信号。 与门的输出端连接到或门。 使用系统，使用适当的相位时钟，并行数据被转换为串行数据。

    Voltage-controlled oscillator resistant to supply voltage noise
    64.
    发明授权
    Voltage-controlled oscillator resistant to supply voltage noise 失效
    电压控制振荡器可抵抗电源电压噪声

    公开(公告)号：US5955929A

    公开(公告)日：1999-09-21

    申请号：US920336

    申请日：1997-08-27

    申请人： Yongsam Moon ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Deog-Kyoon Jeong

    IPC分类号： H03K3/013 ,  H03K3/0231 ,  H03K3/03 ,  H03B5/04 ,  H03B5/24

    CPC分类号： H03K3/0322 ,  H03K3/013 ,  H03K3/0231 ,  H03K3/03

    摘要： A voltage-controlled oscillator (VCO) generates an oscillating signal that is substantially resistant to noise fluctuations in the supply voltage. The VCO is a delay-based VCO which preferably includes a compensation circuit for each delay cell and a noise-immune reference current generator for providing a noise-immune bias current to the conditioning circuit of the VCO. The compensation circuit preferably adjusts the capacitance of the delay cell to compensate for the variations in current caused by the supply noise. The noise-immune reference current generator preferably utilizes a configuration of transistors which maintains through at least one transistor a substantially constant current which is used to bias the conditioning circuit.

    摘要翻译： 压控振荡器（VCO）产生基本上抵抗电源电压中的噪声波动的振荡信号。 VCO是基于延迟的VCO，其优选地包括用于每个延迟单元的补偿电路和用于向VCO的调理电路提供无噪声免疫偏置电流的无噪声免疫参考电流发生器。 补偿电路优选地调整延迟单元的电容以补偿由电源噪声引起的电流变化。 噪声免疫参考电流发生器优选地利用晶体管的配置，晶体管通过至少一个晶体管保持用于偏置调理电路的基本上恒定的电流。

    Method for generating digital communication system clock signals & circuitry for performing that method
    67.
    发明授权
    Method for generating digital communication system clock signals & circuitry for performing that method 失效
    用于产生用于执行该方法的数字通信系统时钟信号和电路的方法

    公开(公告)号：US5574756A

    公开(公告)日：1996-11-12

    申请号：US332561

    申请日：1994-10-31

    申请人： Deog-Kyoon Jeong

    发明人： Deog-Kyoon Jeong

    IPC分类号： H04L7/04 ,  H03L7/081 ,  H03L7/085 ,  H04L7/033 ,  H03D3/24

    CPC分类号： H03L7/085 ,  H03L7/0812 ,  H04L7/0337

    摘要： A clock generating circuit generates 2n clocks (where n is a positive integer number) each having 1/2n frequency of a maximum baud rate of data bit-stream input and a phase difference of .pi./n between successive phases thereof, and simultaneously shifts the phases on the clocks ahead or behind until the phases between the clocks and corresponding data bits of the data bit-stream input are locked in quadrature, by comparing the phase of the clock with those of data bit-stream input and adjusting the phases of the clocks.

    摘要翻译： 时钟发生电路产生2n个数据位流输入的最大波特率的+ E，fra 1/2 + EE n个频率的2n个时钟（n为正整数），连续的 并且同时在前面或后面的时钟上移动相位，直到通过将时钟的相位与数据比特流的相位相比较来将数据比特流输入的时钟和相应数据比特之间的相位锁定在正交上 输入和调整时钟的相位。

    Level-down shifter
    68.
    发明授权
    Level-down shifter 有权
    降档移位器

    公开(公告)号：US08829969B2

    公开(公告)日：2014-09-09

    申请号：US13357654

    申请日：2012-01-25

    申请人： Moon-Sang Hwang ,  Won-Jun Choe ,  Hyun-Chang Kim ,  Deog-Kyoon Jeong

    发明人： Moon-Sang Hwang ,  Won-Jun Choe ,  Hyun-Chang Kim ,  Deog-Kyoon Jeong

    IPC分类号： H03L5/00

    CPC分类号： H03K19/018528

    摘要： A level-down shifter includes: a first load device between a first voltage and a first node; a second load device between the first voltage and a second node; a first input device between the first node and a third node, receiving a reference voltage signal, and adjusting a first node voltage of the first node based on the reference voltage signal; a second input device between the second node and the third node, receiving an input signal, and adjusting a second node voltage of the second node based on the input signal; and a current source between a second voltage and the third node, receiving the second node voltage of the second node, and adjusting a third node voltage of the third node and a bias current based on the second node voltage of the second node, wherein a level of the input signal is higher than the first voltage.

    摘要翻译： 电平降低移位器包括：第一电压和第一节点之间的第一负载装置; 在所述第一电压和第二节点之间的第二负载装置; 在所述第一节点和第三节点之间的第一输入装置，接收参考电压信号，以及基于所述参考电压信号调整所述第一节点的第一节点电压; 在所述第二节点和所述第三节点之间的第二输入设备，接收输入信号，以及基于所述输入信号调整所述第二节点的第二节点电压; 以及第二电压和第三节点之间的电流源，接收第二节点的第二节点电压，以及基于第二节点的第二节点电压调整第三节点的第三节点电压和偏置电流，其中， 输入信号的电平高于第一电压。

    COARSE LOCK DETECTOR
    70.
    发明申请
    COARSE LOCK DETECTOR 有权
    听力锁定检测器

    公开(公告)号：US20120212264A1

    公开(公告)日：2012-08-23

    申请号：US13398532

    申请日：2012-02-16

    申请人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

    发明人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

    IPC分类号： H03L7/00

    CPC分类号： H03L7/095 ,  H03L7/0812 ,  H03L7/101

    摘要： A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.

    摘要翻译： 公开了一种用于延迟锁定环（DLL）的粗略锁定检测器。 粗锁检测器包括多个检测单元。 每个检测单元接收延迟时钟相位和先前检测单元的输出作为输入。 为了增加先前检测单元的输出的时间传播，检测单元被分组排列，使得来自先前检测单元的输出是由多于一个先前检测单元的检测单元生成的。