公开(公告)号：US07985963B2

公开(公告)日：2011-07-26

申请号：US12454698

申请日：2009-05-21

申请人： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Edmond Ward

发明人： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Edmond Ward

IPC分类号： H01L47/00

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/02 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/71 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2481 ,  H01L29/8616 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is either formed or destroyed. It can be formed by either the depletion or excess ions around the tunneling barrier, or by the mobile ions combining with complementary ions. It may be destroyed by either reversing the forming process or by reducing the tunneling barrier and injecting ions into the conductive material. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity multiple states can be created in the memory cell.

摘要翻译： 公开了一种使用具有可变有效宽度的隧道势垒的存储器。 存储元件包括隧道势垒和导电材料。 导电材料通常具有响应于存储元件两端的电压而移动或者远离隧道势垒的移动离子。 形成或破坏低导电性区域。 它可以通过隧道势垒周围的耗尽或过量离子，或通过与互补离子组合的移动离子来形成。 可能通过反转成形过程或减少隧道势垒并将离子注入导电材料来破坏。 低导电率区域增加了隧道势垒的有效宽度，使得电子隧道更大的距离，这降低了存储元件的导电性。 通过改变电导率，可以在存储器单元中产生多个状态。

公开(公告)号：US07394679B2

公开(公告)日：2008-07-01

申请号：US11473005

申请日：2006-06-22

申请人： Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Philip Swab

发明人： Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Kuo-Ren Hsia ,  Steven W. Longcor ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Philip Swab

IPC分类号： G11C11/00

CPC分类号： H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

摘要翻译： 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。

公开(公告)号：US20070158716A1

公开(公告)日：2007-07-12

申请号：US11714555

申请日：2007-03-05

申请人： Darrell Rinerson ,  Steve Hsia ,  Steven Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe Chevallier

发明人： Darrell Rinerson ,  Steve Hsia ,  Steven Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe Chevallier

IPC分类号： H01L29/94 ,  H01L29/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

公开(公告)号：US07038935B2

公开(公告)日：2006-05-02

申请号：US10634636

申请日：2003-08-04

申请人： Darrell Rinerson ,  Wayne Kinney ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Christophe J. Chevallier

发明人： Darrell Rinerson ,  Wayne Kinney ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Christophe J. Chevallier

IPC分类号： G11C11/00 ,  H01L29/02

CPC分类号： G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/165

摘要： A 2-terminal trapped charge memory device is disclosed with voltage switchable multi-level resistance. The trapped charge memory device has a trapped charge memory body sandwiched between two electrodes. The trapped charge memory body can be made of a variety of semiconducting or insulating materials of single-crystalline, poly-crystalline or amorphous structure while containing current carrier traps whose respective energy levels and degrees of carrier occupancy, modifiable by the height and width of an applied write voltage pulse, determine the resistance. The mechanism of modification can be through carrier tunneling, free carrier capturing, trap-hopping conduction or Frenkel-Poole conduction. The current carrier traps can be created with dopant varieties or an initialization procedure.

摘要翻译： 公开了具有可电压切换的多电平电阻的2端子俘获电荷存储器件。 捕获的电荷存储器件具有夹在两个电极之间的俘获电荷存储器体。 捕获的电荷存储器主体可以由单晶，多晶或非晶结构的各种半导体或绝缘材料制成，同时包含其各自的能级和载体占有率的载流子阱，其可由 施加写电压脉冲，确定电阻。 修饰的机制可以通过载体隧穿，自由载体捕获，陷阱跳跃传导或Frenkel-Poole传导。 可以用掺杂剂品种或初始化程序产生当前载体陷阱。

公开(公告)号：US06917539B2

公开(公告)日：2005-07-12

申请号：US10360005

申请日：2003-02-07

申请人： Darrell Rinerson ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Wayne Kinney

发明人： Darrell Rinerson ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Wayne Kinney

IPC分类号： G11C11/56 ,  G11C13/00 ,  G11C11/14

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77

摘要： High density NVRAM. An array of memory cells capable of storing at least a megabit of information, each memory cell including a memory plug that includes a memory element that switches from a first resistance state to a second resistance state upon application of a first write voltage of a first polarity and reversibly switches from the second resistance state to the first resistance state upon application of a second write voltage of polarity opposite to the first polarity.

摘要翻译： 高密度NVRAM。 一种能够存储至少一兆位信息的存储器单元阵列，每个存储器单元包括存储器插件，该存储器插件包括存储元件，该存储器元件在施加第一极性的第一写入电压时从第一电阻状态切换到第二电阻状态 并且当施加与第一极性相反的极性的第二写入电压时，可逆地从第二电阻状态切换到第一电阻状态。

公开(公告)号：US06906939B2

公开(公告)日：2005-06-14

申请号：US10612191

申请日：2003-07-01

申请人： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward

发明人： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward

IPC分类号： G11C11/56 ,  G11C13/00 ,  G11C16/02 ,  H01L27/24 ,  G11C5/06

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31

摘要： A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

公开(公告)号：US06870755B2

公开(公告)日：2005-03-22

申请号：US10604556

申请日：2003-07-30

申请人： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

发明人： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

IPC分类号： G11C13/00 ,  G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/77

摘要： A re-writable memory that uses resistive memory cell elements with non-linear IV characteristics is disclosed. Non-linearity is important in certain memory arrays to prevent unselected cells from being disturbed and to reduce the required current. Non-linearity refers to the ability of the element to block the majority of current up to a certain level, but then, once that level is reached, the element allows the majority of the current over and above that level to flow.

摘要翻译： 公开了一种使用具有非线性IV特性的电阻性存储单元元件的可重写存储器。 在某些存储器阵列中非线性是重要的，以防止未选择的单元被干扰并减少所需的电流。 非线性是指元件将大多数电流阻塞到一定水平的能力，但是，一旦达到该电平，该元件允许超过该电平的大部分电流流动。

公开(公告)号：US06753561B1

公开(公告)日：2004-06-22

申请号：US10330512

申请日：2002-12-26

申请人： Darrell Rinerson ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Christophe J. Chevallier

发明人： Darrell Rinerson ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Christophe J. Chevallier

IPC分类号： H01L31062

CPC分类号： H01L27/2418 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/165

摘要： Cross point memory array using multiple thin films. The invention is a cross point memory array that uses conductive array lines and multiple thin films as a memory plug. The thin films of the memory plug include a memory element and a non-ohmic device. The memory element switches between resistive states upon application of voltage pulses and the non-ohmic device imparts a relatively high resistance to the memory plug upon application of low magnitude voltages.

摘要翻译： 使用多个薄膜的交叉点存储阵列。 本发明是使用导电阵列线和多个薄膜作为存储器插头的交叉点存储器阵列。 存储器插头的薄膜包括存储器元件和非欧姆器件。 存储器元件在施加电压脉冲时在电阻状态之间切换，并且非欧姆器件在施加低幅度电压时对存储器插头施加相当高的电阻。