公开(公告)号：US20060245243A1

公开(公告)日：2006-11-02

申请号：US11473005

申请日：2006-06-22

申请人： Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Hsia ,  Steven Longcor ,  Christophe Chevallier ,  John Sanchez ,  Philip Swab

发明人： Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Hsia ,  Steven Longcor ,  Christophe Chevallier ,  John Sanchez ,  Philip Swab

IPC分类号： G11C11/14

CPC分类号： H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

公开(公告)号：US20050174835A1

公开(公告)日：2005-08-11

申请号：US10773549

申请日：2004-02-06

申请人： Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Hsia ,  Steven Longcor ,  Christophe Chevallier ,  John Sanchez ,  Philip Swab

发明人： Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Hsia ,  Steven Longcor ,  Christophe Chevallier ,  John Sanchez ,  Philip Swab

IPC分类号： G11C11/16 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  G11C11/14

CPC分类号： H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

摘要翻译： 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。

公开(公告)号：US20050101086A1

公开(公告)日：2005-05-12

申请号：US10605963

申请日：2003-11-10

申请人： Darrell Rinerson ,  Steve Hsia ,  Steven Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe Chevallier

发明人： Darrell Rinerson ,  Steve Hsia ,  Steven Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe Chevallier

IPC分类号： G11C11/56 ,  G11C13/00 ,  H01L21/8246 ,  H01L27/115 ,  H01L41/24 ,  H01L21/336

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face with a second surface area and the multi-resistive state element has a bottom face with a third surface area and a top face with a fourth surface area. The multi-resistive state element's bottom face is in contact with the bottom electrode's top face and the multi-resistive state element's top face is in contact with the top electrode's bottom face. Furthermore, the fourth surface area is not equal to the second surface area.

摘要翻译： 提供导电存储器堆叠。 存储器堆叠包括底电极，顶电极和夹在电极之间的多电阻状态元件。 底电极可以被描述为具有第一表面区域的顶面，顶电极具有具有第二表面区域的底面，并且多电阻状态元件具有带有第三表面区域的底面和顶面 第四表面积。 多电阻状态元件的底面与底部电极的顶面接触，并且多电阻状态元件的顶面与顶部电极的底面接触。 此外，第四表面积不等于第二表面积。

公开(公告)号：US20050013172A1

公开(公告)日：2005-01-20

申请号：US10921037

申请日：2004-08-17

申请人： Darrell Rinerson ,  Christophe Chevallier ,  Steven Longcor ,  Edmond Ward ,  Wayne Kinney ,  Steve Hsia

发明人： Darrell Rinerson ,  Christophe Chevallier ,  Steven Longcor ,  Edmond Ward ,  Wayne Kinney ,  Steve Hsia

IPC分类号： G11C11/56 ,  G11C13/00 ,  G11C8/00

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  G11C2213/77

摘要： Multiple modes of operation in a cross point array. The invention is a cross point array that uses a read voltage across a conductive array line pair during a read mode. The read voltage produces a read current that is indicative of a first program state when the read current is at a first level and indicative of a second program state when the read current is at a second level. The read current is ineffective to produce a change in program state. A first voltage pulse is used during a first write mode if a change from a second program state to a first program state is desired. A second voltage pulse is used during a second write mode if a change from the first program state to the second program state is desired.

公开(公告)号：US20070158716A1

公开(公告)日：2007-07-12

申请号：US11714555

申请日：2007-03-05

申请人： Darrell Rinerson ,  Steve Hsia ,  Steven Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe Chevallier

发明人： Darrell Rinerson ,  Steve Hsia ,  Steven Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe Chevallier

IPC分类号： H01L29/94 ,  H01L29/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

公开(公告)号：US20060171200A1

公开(公告)日：2006-08-03

申请号：US11095026

申请日：2005-03-30

申请人： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Steven Longcor ,  John Sanchez ,  Lawrence Schloss ,  Philip Swab ,  Edmond Ward

发明人： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Steven Longcor ,  John Sanchez ,  Lawrence Schloss ,  Philip Swab ,  Edmond Ward

IPC分类号： G11C11/34

CPC分类号： H01L45/08 ,  G06F17/5045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/005 ,  G11C2013/009 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625

摘要： A memory using a mixed valence conductive oxides. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

摘要翻译： 使用混合价态导电氧化物的记忆。 存储器包括在其缺氧状态下导电性较差的混合价态导电氧化物和作为电解质的氧的混合电子离子导体并且促进有效引起氧离子运动的电场。

公开(公告)号：US08675389B2

公开(公告)日：2014-03-18

申请号：US13272985

申请日：2011-10-13

申请人： Christophe Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez, Jr. ,  Philip Swab ,  Edmond Ward

发明人： Christophe Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez, Jr. ,  Philip Swab ,  Edmond Ward

IPC分类号： G11C11/21

CPC分类号： H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

摘要： A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

摘要翻译： 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。

公开(公告)号：US08611130B2

公开(公告)日：2013-12-17

申请号：US13301490

申请日：2011-11-21

申请人： Darrell Rinerson ,  Christophe Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  John Sanchez, Jr. ,  Philip Swab ,  Edmond Ward

发明人： Darrell Rinerson ,  Christophe Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  John Sanchez, Jr. ,  Philip Swab ,  Edmond Ward

IPC分类号： H01L21/64 ,  G11C11/21

CPC分类号： H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

摘要翻译： 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。

公开(公告)号：US20050231992A1

公开(公告)日：2005-10-20

申请号：US11151880

申请日：2005-06-13

申请人： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Steven Longcor ,  Edmond Ward

发明人： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Steven Longcor ,  Edmond Ward

IPC分类号： G11C11/56 ,  G11C13/00 ,  G11C16/02 ,  H01L27/24 ,  G11C5/00

CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31

摘要： A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

摘要翻译： 具有多个内存层的可重写内存。 只要存在只有一个选择了两个端子的存储单元，就可以选择使用层叠交叉点结构中的存储单元的两个端子进行选择，以便选择多层导电线。 通过多层共享逻辑可以重新使用驱动程序集。

公开(公告)号：US20050111263A1

公开(公告)日：2005-05-26

申请号：US11012059

申请日：2004-12-13

申请人： Darrell Rinerson ,  Steven Longcor ,  Christophe Chevallier ,  Edmond Ward

发明人： Darrell Rinerson ,  Steven Longcor ,  Christophe Chevallier ,  Edmond Ward

IPC分类号： G11C11/56 ,  G11C13/00 ,  G11C11/34

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/77

摘要： Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines being uniquely defined. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage can be approximately equal to the average of the first select voltage and the second select voltage.

摘要翻译： 交叉点存储器阵列使用不同的电压。 本发明是一种交叉点存储器阵列，其在一个导电阵列线上施加第一选择电压，在第二导电阵列线上施加第二选择电压，两个导电阵列线是唯一限定的。 此外，未选择的电压被施加到未选择的导电阵列线。 可以在选择过程之前，之后或期间施加取消选择电压。 非选择电压可以近似等于第一选择电压和第二选择电压的平均值。