Methods for forming optoelectronic devices including heterojunction

    公开(公告)号:US09082919B2

    公开(公告)日:2015-07-14

    申请号:US13451439

    申请日:2012-04-19

    摘要: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

    Methods for forming optoelectronic devices including heterojunction

    公开(公告)号:US09048366B2

    公开(公告)日:2015-06-02

    申请号:US13451439

    申请日:2012-04-19

    摘要: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

    Optoelectronic devices including heterojunction and intermediate layer
    65.
    发明授权
    Optoelectronic devices including heterojunction and intermediate layer 有权
    包括异质结和中间层的光电器件

    公开(公告)号:US09136418B2

    公开(公告)日:2015-09-15

    申请号:US13451455

    申请日:2012-04-19

    摘要: Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.

    摘要翻译: 实施例通常涉及诸如太阳能电池的光电半导体器件。 在一个方面,器件包括由砷化镓(GaAs)制成并且仅具有一种掺杂类型的吸收层。 发射极层位于比器件的背面靠近吸收体层,并且由不同的材料制成并具有比吸收层更高的带隙。 在发射极层和吸收层之间形成异质结,并且在偏离异质结的位置处,在发射极层和吸收层之间形成p-n结,并且至少部分地在不同的材料内形成p-n结。 中间层位于吸收层和发射极层之间,并且提供p-n结与异质结的偏移,并且包括渐变层和未分级的后窗层。

    Methods for forming optoelectronic devices including heterojunction

    公开(公告)号:US09136417B2

    公开(公告)日:2015-09-15

    申请号:US13451439

    申请日:2012-04-19

    摘要: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

    METHOD AND SYSTEM FOR A GAN VERTICAL JFET WITH SELF-ALIGNED SOURCE METALLIZATION
    68.
    发明申请
    METHOD AND SYSTEM FOR A GAN VERTICAL JFET WITH SELF-ALIGNED SOURCE METALLIZATION 有权
    具有自对准源金属化的GAN垂直JFET的方法和系统

    公开(公告)号:US20130299882A1

    公开(公告)日:2013-11-14

    申请号:US13468332

    申请日:2012-05-10

    IPC分类号: H01L29/80 H01L21/20

    摘要: A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.

    摘要翻译: 半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底的沟道结构。 沟道结构包括第一III族氮化物外延材料,其特征在于一个或多个沟道侧壁。 半导体器件还包括耦合到沟道结构的源极区域。 源区包括第二III族氮化物外延材料。 所述半导体器件还包括耦合到所述一个或多个沟道侧壁的III族氮化物栅极结构,与所述III族氮化物栅极结构电接触的栅极金属结构以及覆盖所述栅极金属结构的至少一部分的介电层。 电介质层的顶表面与源区的顶表面基本上共面。

    METHOD AND SYSTEM FOR A GAN VERTICAL JFET WITH SELF-ALIGNED GATE METALLIZATION
    69.
    发明申请
    METHOD AND SYSTEM FOR A GAN VERTICAL JFET WITH SELF-ALIGNED GATE METALLIZATION 有权
    具有自对准栅极金属化的GAN垂直JFET的方法和系统

    公开(公告)号:US20130299873A1

    公开(公告)日:2013-11-14

    申请号:US13468325

    申请日:2012-05-10

    IPC分类号: H01L29/80 H01L21/335

    摘要: A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.

    摘要翻译: 半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底并且包括漂移区,沟道区和延伸区的第一III族氮化物外延层。 沟道区域通过漂移区域与III族氮化物衬底分离。 通道区域的特征在于第一宽度。 延伸区域通过沟道区域与漂移区域分离。 延伸区域的特征在于小于第一宽度的第二宽度。 半导体器件还包括耦合到延伸区域的顶表面的第二III族氮化物外延层,耦合到沟道区域的侧壁并相对于延伸区域横向自对准的III族氮化物栅极结构,以及 栅极金属结构与III族氮化物栅极结构电接触并且相对于延伸区域横向自对准。

    Method and system for a gallium nitride vertical JFET with self-aligned gate metallization
    70.
    发明授权
    Method and system for a gallium nitride vertical JFET with self-aligned gate metallization 有权
    具有自对准栅极金属化的氮化镓垂直JFET的方法和系统

    公开(公告)号:US08716078B2

    公开(公告)日:2014-05-06

    申请号:US13468325

    申请日:2012-05-10

    IPC分类号: H01L21/337

    摘要: A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.

    摘要翻译: 半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底并且包括漂移区,沟道区和延伸区的第一III族氮化物外延层。 沟道区域通过漂移区域与III族氮化物衬底分离。 通道区域的特征在于第一宽度。 延伸区域通过沟道区域与漂移区域分离。 延伸区域的特征在于小于第一宽度的第二宽度。 半导体器件还包括耦合到延伸区域的顶表面的第二III族氮化物外延层,耦合到沟道区域的侧壁并相对于延伸区域横向自对准的III族氮化物栅极结构,以及 栅极金属结构与III族氮化物栅极结构电接触并且相对于延伸区域横向自对准。