公开(公告)号：US11804257B2

公开(公告)日：2023-10-31

申请号：US17992726

申请日：2022-11-22

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Brian P. Callaway

IPC: G11C11/40 ,  G11C11/4074 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/525 ,  G11C11/22 ,  G06F13/16

CPC classification number: G11C11/4074 ,  G06F13/1668 ,  G11C11/2297 ,  H01L23/5252 ,  H01L23/5256 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/1427 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.

公开(公告)号：US11687406B2

公开(公告)日：2023-06-27

申请号：US17854331

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/1052 ,  G06F11/1056 ,  G06F11/1072

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

公开(公告)号：US11676052B2

公开(公告)日：2023-06-13

申请号：US16849819

申请日：2020-04-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  James S. Rehmeyer ,  Brett K. Dodds ,  Anthony D. Veches ,  Libo Wang ,  Di Wu

IPC: G06N5/047 ,  G06N20/00 ,  H04L67/12 ,  H04L67/10 ,  H04L9/40 ,  G16Y10/75

CPC classification number: G06N5/047 ,  G06N20/00 ,  H04L63/1408 ,  H04L67/10 ,  H04L67/12 ,  G16Y10/75

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods for an internet of things (IoT) system to include edge devices that perform at least some functions without communicating with a cloud computing system. An edge device may include a memory with on-memory pattern matching capabilities. The edge device may perform pattern matching operations on data collected by the edge device or sensors in communication with the edge device. Based on results of the pattern matching operations, the edge device may perform various functions, such as transmitting data to the cloud computing system, activating an alarm, and/or changing a frequency at which data is transmitted.

公开(公告)号：US11664084B2

公开(公告)日：2023-05-30

申请号：US17391830

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Randall J. Rooney ,  Debra M. Bell

IPC: G11C29/42 ,  G11C29/18 ,  G11C29/14 ,  G11C29/44 ,  G06F11/07 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F11/0754 ,  G06F11/106 ,  G11C29/14 ,  G11C29/18 ,  G11C29/4401

Abstract: Methods, devices, and systems related to memory device on-die ECC data are described. In an example, a scrub operation can be performed on data in order to determine which rows of memory cells in an array include a particular number of errors. The particular number of errors can be a number of errors that exceed a threshold number of errors. An address of the determined rows with the particular number of errors can be stored in memory cells of the array for later access. The address of the determined rows can be accessed to perform a user-initiated repair operation, a self-repair operation, a refresh operation, and/or to alter timing of access of the cells or alter voltage of the cells.

公开(公告)号：US20230048317A1

公开(公告)日：2023-02-16

申请号：US17400886

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Brian P. Callaway

IPC: G11C11/4074 ,  H01L25/065 ,  H01L23/00

Abstract: Methods, systems, and devices for dynamic power distribution for stacked memory are described. A stacked memory device may include switching components that support dynamic coupling between a shared power source of the memory device and circuitry associated with operating memory arrays of respective memory dies. In some examples, such techniques include coupling a power source with array circuitry based on an access activity or a degree of access activity for the array circuitry. In some examples, such techniques include isolating a power source from array circuitry based on a lack of access activity or a degree of access activity for the array circuitry. The dynamic coupling or isolation may be supported by various signaling of the memory device, such as signaling between memory dies, signaling between a memory die and a central controller, or signaling between the memory device and a host device.

公开(公告)号：US20230031842A1

公开(公告)日：2023-02-02

申请号：US17391830

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Randall J. Rooney ,  Debra M. Bell

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C29/18

Abstract: Methods, devices, and systems related to memory device on-die ECC data are described. In an example, a scrub operation can be performed on data in order to determine which rows of memory cells in an array include a particular number of errors. The particular number of errors can be a number of errors that exceed a threshold number of errors. An address of the determined rows with the particular number of errors can be stored in memory cells of the array for later access. The address of the determined rows can be accessed to perform a user-initiated repair operation, a self-repair operation, a refresh operation, and/or to alter timing of access of the cells or alter voltage of the cells.

公开(公告)号：US11532358B2

公开(公告)日：2022-12-20

申请号：US16553821

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Debra M. Bell ,  James S. Rehmeyer ,  Robert Bunnell ,  Nathaniel J. Meier

IPC: G11C11/40 ,  G11C14/00 ,  G11C17/18 ,  G11C11/4072 ,  G11C11/4096 ,  G11C17/16

Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells and a fuse array configured to store precondition data. The precondition data can identify a portion of the memory array, specify a predetermined precondition state, or a combination thereof. When the memory device powers on, the memory device can be configured to automatically retrieve the precondition data from the fuse array and/or to write memory cells in the portion of the memory array to the predetermined precondition state before executing an access command.

公开(公告)号：US11410713B2

公开(公告)日：2022-08-09

申请号：US16840946

申请日：2020-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Di Wu ,  Debra M. Bell ,  Anthony D. Veches ,  James S. Rehmeyer ,  Libo Wang

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/406

Abstract: Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

公开(公告)号：US20220189540A1

公开(公告)日：2022-06-16

申请号：US17684235

申请日：2022-03-01

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

公开(公告)号：US11239200B2

公开(公告)日：2022-02-01

申请号：US16391804

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/64 ,  H01L25/00 ,  H01L23/00

Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.