公开(公告)号：US10043587B2

公开(公告)日：2018-08-07

申请号：US15215423

申请日：2016-07-20

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  William O'Leary

IPC: G11C29/16 ,  H03K19/173 ,  G11C8/10 ,  G11C7/22 ,  G11C8/08 ,  G11C29/00 ,  G11C7/10 ,  G11C8/06 ,  G11C29/46

Abstract: Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.

公开(公告)号：US20180122439A1

公开(公告)日：2018-05-03

申请号：US15857597

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Kallol Mazumder

IPC: G11C7/22 ,  G06F9/30 ,  G11C7/10

CPC classification number: G11C7/22 ,  G06F9/30156 ,  G11C7/109 ,  G11C2207/2272

Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

公开(公告)号：US20170366188A1

公开(公告)日：2017-12-21

申请号：US15684734

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder

IPC: H03K21/40 ,  G11C7/10 ,  H03K19/21 ,  H03K21/10

CPC classification number: H03K21/40 ,  G06F5/06 ,  G11C7/1087 ,  G11C7/109 ,  G11C8/06 ,  H03K19/21 ,  H03K21/10

Abstract: Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

公开(公告)号：US20160314824A1

公开(公告)日：2016-10-27

申请号：US15203665

申请日：2016-07-06

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder

IPC: G11C7/22 ,  G11C8/10

CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C8/10 ,  G11C2207/2272

Abstract: Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. The command path decodes the command and provides an output command signal responsive to the clock signal. The method further includes providing an inactive clock signal to the command path for a second portion of the command cycle for the command of the back-to-back commands.

公开(公告)号：US20150340072A1

公开(公告)日：2015-11-26

申请号：US14285476

申请日：2014-05-22

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/225

Abstract: Apparatuses and methods for providing a command to a data block are described. An example apparatus includes a command circuit configured to provide a command signal in an internal clock time domain based at least in part on a memory access command received in an external clock time domain. The example apparatus further includes a command path delay configured to delay the command signal. The example apparatus further includes a data strobe generator circuit configured to receive the command signal and a data strobe signal. A plurality of clock edges of the data strobe signal correspond to received data bits associated with the memory access command. The data strobe generator circuit is configured to control input circuitry to capture the data associated with the memory access command based at least in part on the data strobe signal and the command signal.

Abstract translation: 描述用于向数据块提供命令的装置和方法。 一种示例性装置包括命令电路，其被配置为至少部分地基于在外部时钟时域中接收的存储器访问命令来在内部时钟时域中提供命令信号。 示例设备还包括被配置为延迟命令信号的命令路径延迟。 该示例设备还包括数据选通发生器电路，被配置为接收命令信号和数据选通信号。 数据选通信号的多个时钟边缘对应于与存储器访问命令相关联的接收数据位。 数据选通发生器电路被配置为至少部分地基于数据选通信号和命令信号来控制输入电路以捕获与存储器访问命令相关联的数据。

公开(公告)号：US09183904B2

公开(公告)日：2015-11-10

申请号：US14175897

申请日：2014-02-07

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Donald M. Morgan

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093

Abstract: Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path are described. In an example shared signal path, a command circuit is configured to receive a command and an indicator signal. A lockout circuit is coupled to the command circuit and configured to give precedence to a chosen command type by masking the indicator signal. In another example, a counter circuit is coupled to the lockout circuit and configured to force the lockout circuit to sample the indicator signal at regular intervals.

Abstract translation: 描述了使用共享信号路径促进内部命令分割的装置，存储器和方法。 在示例性共享信号路径中，命令电路被配置为接收命令和指示符信号。 锁定电路耦合到命令电路并且被配置为通过掩蔽指示符信号来优先选择所选择的命令类型。 在另一示例中，计数器电路耦合到锁定电路并且被配置为强制锁定电路以规则的间隔对指示符信号进行采样。

公开(公告)号：US20150228317A1

公开(公告)日：2015-08-13

申请号：US14175897

申请日：2014-02-07

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Donald M. Morgan

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093

Abstract: Apparatuses, memories, and methods for facilitating splitting of internal commands using a shared signal path are described. In an example shared signal path, a command circuit is configured to receive a command and an indicator signal. A lockout circuit is coupled to the command circuit and configured to give precedence to a chosen command type by masking the indicator signal. In another example, a counter circuit is coupled to the lockout circuit and configured to force the lockout circuit to sample the indicator signal at regular intervals.

Abstract translation: 描述了使用共享信号路径促进内部命令分割的装置，存储器和方法。 在示例性共享信号路径中，命令电路被配置为接收命令和指示符信号。 锁定电路耦合到命令电路并且被配置为通过掩蔽指示符信号来优先选择所选择的命令类型。 在另一示例中，计数器电路耦合到锁定电路并且被配置为强制锁定电路以规则的间隔对指示符信号进行采样。

公开(公告)号：US09000817B2

公开(公告)日：2015-04-07

申请号：US14046796

申请日：2013-10-04

Applicant: Micron Technology, Inc

Inventor： Jongtae Kwak ,  Kallol Mazumder

IPC: H03L7/00 ,  H03L7/08 ,  H03L7/081

CPC classification number: H03L7/08 ,  H03L7/0816

Abstract: Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.

Abstract translation: 公开了与改变用于执行命令的命令信号的定时相关的装置和方法。 一种这样的方法包括根据由时钟电路提供的输出时钟信号的时钟周期的数量来计算时钟电路的前向路径延迟，并将多个延迟的附加时钟周期与信号路径的前向路径延迟相加 。 时钟电路的正向路径延迟表示信号路径的前向路径延迟，并且附加时钟周期的数量至少部分地基于前向路径延迟的时钟周期数。

公开(公告)号：US20240069589A1

公开(公告)日：2024-02-29

申请号：US17897957

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Navya Sri Sreeram ,  Scott E. Smith

IPC: G06F1/08 ,  G06F1/10

CPC classification number: G06F1/08 ,  G06F1/10

Abstract: An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.

公开(公告)号：US11804251B2

公开(公告)日：2023-10-31

申请号：US18174545

申请日：2023-02-24

Applicant: Micron Technology, Inc.

Inventor： Navya Sri Sreeram ,  Kallol Mazumder

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1009 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/1093

Abstract: A memory device includes a command interface configured to receive a two-cycle command from a host device via multiple command address bits. The memory device also includes a command decoder configured to decode a first portion of the multiple command address bits in a first cycle of the two-cycle command. The command decoder includes mask circuitry. The mask circuitry includes mask generation circuitry configured to generate a mask signal. The mask circuitry also includes multiplexer circuitry configured to apply the mask signal to block the command decoder from decoding a second portion of the multiple command address bits in a second cycle of the two-cycle command.