公开(公告)号：US12254949B2

公开(公告)日：2025-03-18

申请号：US18314153

申请日：2023-05-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

IPC: G11C7/00 ,  G11C5/06 ,  G11C7/06 ,  G11C16/08 ,  H01L23/00 ,  H01L25/065 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B80/00

Abstract: A memory device, such as a three-dimensional AND or NOR flash memory, includes a first chip and a second chip. The first chip has multiple source line switches, multiple bit line switches, multiple page buffers, and multiple sensing amplifiers. The first chip has multiple first pads. The second chip has multiple memory cells to form multiple memory cell blocks. Multiple second pads are on a first surface of the second chip to be respectively coupled to multiple local bit lines and multiple local source lines of the memory cell blocks. Each of the first pads is coupled to the corresponding second pads.

公开(公告)号：US12073883B2

公开(公告)日：2024-08-27

申请号：US17742148

申请日：2022-05-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Teng-Hao Yeh ,  Chih-Chang Hsieh

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A ternary content addressable memory, disposed in a stacked memory device, includes a first memory cell string and a second memory cell string. The first memory cell string is coupled between a matching line and a first source line and receives multiple first word line signals. The first memory cell string has a first memory cell string selection switch controlled by a first search signal. The second memory cell string is coupled between the matching line and a second source line and receives multiple second word line signals. The second memory cell string has a second memory cell string selection switch controlled by a second search signal.

公开(公告)号：US20240121954A1

公开(公告)日：2024-04-11

申请号：US17963202

申请日：2022-10-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  H01L27/1157

Abstract: A memory device includes a first stack structure including first gate layers and first insulating layers alternately stacked with each other. A first channel pillar extends through the first stack structure. A second stack structure is located on the first stack structure and includes second gate layers and second insulating layers alternately stacked with each other. A second channel pillar extends through the second stack structure and is separated from the first channel pillar. A first conductive pillar and a second conductive pillar are located in and electrically connecting with the first channel pillar and the second channel pillar. A charge storage structure is located between the first gate layers and the first channel pillar, and between the second gate layers and the second channel pillar. The memory device may be applied to a 3D AND flash memory.

公开(公告)号：US11894065B2

公开(公告)日：2024-02-06

申请号：US17569424

申请日：2022-01-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Tzu-Hsuan Hsu

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: A three-dimensional memory device, such as 3D AND Flash memory device, includes a first page buffer, a second page buffer, a sense amplifier, a first path selector, and a second path selector. The first page buffer and the second page buffer are respectively configured to temporarily store a first write-in data and a second write-in data. The first path selector couples the sense amplifier or the first page buffer to a first global bit line according to a first control signal. The second path selector couples the sense amplifier or the second page buffer to a second global bit line according to a second control signal.

公开(公告)号：US20240028211A1

公开(公告)日：2024-01-25

申请号：US18161900

申请日：2023-01-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Teng-Hao Yeh ,  Chih-Chang Hsieh ,  Chun-Hsiung Hung ,  Yung-Chun LI

IPC: G06F3/06 ,  G11C16/28

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/28

Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

公开(公告)号：US11844221B2

公开(公告)日：2023-12-12

申请号：US17409431

申请日：2021-08-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Li-Yen Liang ,  Teng-Hao Yeh

IPC: H10B43/35 ,  H10B43/10 ,  H10B43/40 ,  H01L23/522 ,  H10B43/27

CPC classification number: H10B43/35 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A 3D flash memory device such as a 3D AND flash memory device is provided. The 3D flash memory device includes a substrate, a conductive layer, a 3D flash memory array, and through-array vias (TAVs). The substrate includes a memory cell region and a passive device region. The conductive layer is formed on the substrate, and the conductive layer includes: a first circuit disposed at the memory cell region and a second circuit of a passive device disposed at the passive device region. The 3D flash memory array is formed on the first circuit of the memory cell region. The TAVs are respectively formed on the second circuit of the passive device disposed at the passive device region and connected to at least one end of the second circuit.

公开(公告)号：US11825654B2

公开(公告)日：2023-11-21

申请号：US17113190

申请日：2020-12-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H10B43/27 ,  H01L21/768 ,  G11C16/08

CPC classification number: H10B43/27 ,  G11C16/08 ,  H01L21/76885

Abstract: A memory device includes a stacked structure and at least one first element structure. The stacked structure is in a memory array region and a staircase contact region. The stacked structure includes first conductive layers and a second conductive layer arranged in a longitudinal direction. The memory array region and the staircase contact region are arranged in a first lateral direction. The at least one first element structure passes through the first conductive layers and the second conductive layer along the longitudinal direction. The first conductive layers surround a sidewall surface of the at least one first element structure. The second conductive layer includes conductive portions arranged in a second lateral direction. The conductive portions are completely separated from each other by the at least one first element structure. The first lateral direction is different from the second lateral direction.

公开(公告)号：US11778823B2

公开(公告)日：2023-10-03

申请号：US17125407

申请日：2020-12-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Guan-Ru Lee

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: The present disclosure provides a three-dimensional memory device and a method for manufacturing the same. The three-dimensional memory device includes a plurality of tiles, and each tiles includes a plurality of blocks, and each blocks includes a gate stacked structure, a conductive layer, first ring-shaped channel pillars, source/drain pillars, and charge storage structures. The gate stacked structure is disposed on the substrate and includes gate layers electrically insulated from each other. The conductive layer is disposed between the substrate and the gate stacked structure. The first ring-shaped channel pillars are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate, and each of the first ring-shaped channel pillars are configured with two source/drain pillars disposed therein. Each of the charge storage structures is disposed between the corresponding gate layer and the corresponding first ring-shaped channel pillar. The conductive layer in one of the tiles is isolated from the conductive layers in the other tiles.

公开(公告)号：US20230225126A1

公开(公告)日：2023-07-13

申请号：US17575418

申请日：2022-01-13

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Chia-Jung Chiu ,  Teng-Hao Yeh ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.

公开(公告)号：US11631461B2

公开(公告)日：2023-04-18

申请号：US17477205

申请日：2021-09-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh

IPC: G11C16/08 ,  G11C5/02 ,  G11C8/14 ,  H01L23/522 ,  H01L23/528

Abstract: A three dimension memory device including a plurality of word lines, a plurality of first switches, a plurality of second switches and N conductive wire layers is provided, where N is a positive integer larger than 1. The word lines are divided into a plurality of word line groups. The first switches receive a common word line voltage. The second switches receive a reference ground voltage. A first word line group is connected to a first conductive wire layer through a second conductive wire layer. An ith word line group is connected to the first conductive wire layer through an (i+1)th to the second conductive wire layer in sequence.