公开(公告)号：US5629218A

公开(公告)日：1997-05-13

申请号：US278681

申请日：1994-07-21

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/786 ,  H01L21/265

CPC classification number: H01L29/66765 ,  H01L21/28 ,  H01L29/78618

Abstract: A thin film transistor and method for forming the same are disclosed. The transistor comprises a gate conductor (14) and a gate insulator (16). A semiconductor channel layer (18) is formed adjacent the gate insulator (16). A mask block (22) is formed covering a channel region (30) in the channel layer (18). A source region (26) and a drain region (28) are formed in the channel layer (18) adjacent opposite ends of the mask block (22). Conductive bodies (32) and (34) are formed in contact with source region (26) and drain region (28), respectively. Electric contacts (42) and (44) are then formed in contact with conductive bodies (32) and (34), respectively.

Abstract translation: 公开了一种薄膜晶体管及其形成方法。 晶体管包括栅极导体（14）和栅极绝缘体（16）。 在栅极绝缘体（16）附近形成半导体沟道层（18）。 掩模块（22）被形成为覆盖沟道层（18）中的沟道区（30）。 源极区域（26）和漏极区域（28）形成在与掩模块（22）的相对端相邻的沟道层（18）中。 导电体（32）和（34）分别形成为与源区（26）和漏区（28）接触。 然后，电触点（42）和（44）分别与导电体（32）和（34）接触形成。

公开(公告)号：US5548548A

公开(公告)日：1996-08-20

申请号：US358647

申请日：1994-12-19

Applicant: Amitava Chatterjee ,  Jiann Liu ,  Purnendu Mozumder ,  Mark S. Rodder ,  Ih-Chin Chen

Inventor： Amitava Chatterjee ,  Jiann Liu ,  Purnendu Mozumder ,  Mark S. Rodder ,  Ih-Chin Chen

IPC: H01L29/78 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/10 ,  H01L29/423 ,  G11C11/401

CPC classification number: H01L27/10873 ,  G11C11/404 ,  H01L29/1087 ,  H01L29/42364 ,  H01L29/42376

Abstract: A design to attain a pass transistor for a 256 Mbit DRAM part. The transistor having a gate length of about 0.3 .mu.m, a t.sub.ox of about 85 .ANG., which is much thicker than the .about.65 .ANG. t.sub.ox for 0.25 .mu.m logic technology, a V.sub.WL of 3.75 V, a V.sub.sub of -1 V, arsenic LDD and a boron concentration in the channel region of about 2.7.times.10.sup.17 /cm.sup.3 are the desired technological choices for 256 Mbit DRAM devices.

Abstract translation: 实现256 Mbit DRAM器件的传输晶体管的设计。 栅极长度约为0.3μm的晶体管，约为85安培的毒素，其比0.25微米逻辑技术的DIFFERENCE 65 ANGSTROM毒is厚，V VL为3.75伏，Vsub为-1伏，砷 LDD和沟道区域中的硼浓度约为2.7x1017 / cm3，是256 Mbit DRAM器件的理想选择。

公开(公告)号：US5504359A

公开(公告)日：1996-04-02

申请号：US369851

申请日：1995-01-06

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L27/108 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/7827 ,  H01L29/1033 ,  H01L29/66666 ,  H01L29/4236

Abstract: This is a vertical MOSFET device with low gate to source overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24,26 of a second conductivity type formed in the upper surface of the substrate 22; a vertical pillar with a channel region 28 of the first conductivity type, a lightly doped drain region 30 of the second conductivity type and a highly doped drain contact region 32 of the second conductivity type; a gate insulator 34, a gate electrode 36 surrounding the vertical pillar, and an insulating spacer 38 between the source 24,26 and a portion of the gate 36 regions. This is also a method of forming a vertical MOSFET device on a single crystal semiconductor substrate, with the device having a pillar on the substrate, with the pillar having a channel region in a lower portion and with the channel region having a top and a highly doped first source/drain region in an upper portion of the pillar, with the substrate having a highly doped second source/drain region and with a gate insulator on the substrate and on the pillar. The method comprises: isotropically forming a first gate electrode material layer on the pillar and the substrate; anisotropically etching the first gate electrode material leaving a vertical portion of gate electrode material on the pillar; anisotropically depositing an insulating spacer; and conformally depositing a second gate electrode material layer.

Abstract translation: 这是具有低栅极到源极重叠电容的垂直MOSFET器件。 它可以包括第一导电类型的半导体衬底22，形成在衬底22的上表面中的第二导电类型的源区24,26; 具有第一导电类型的沟道区28的垂直柱，第二导电类型的轻掺杂漏极区30和第二导电类型的高掺杂漏极接触区32; 栅极绝缘体34，围绕垂直柱的栅电极36和源24,26与栅极36区域的一部分之间的绝缘间隔物38。 这也是在单晶半导体衬底上形成垂直MOSFET器件的方法，其中该器件在衬底上具有一个柱，其中该柱在下部具有沟道区，并且沟道区具有顶部和高度 掺杂的第一源极/漏极区域，其中衬底具有高度掺杂的第二源极/漏极区域，并且在衬底上和栅极上具有栅极绝缘体。 该方法包括：在柱和衬底上各向同性地形成第一栅电极材料层; 各向异性地蚀刻第一栅电极材料，留下柱上的栅电极材料的垂直部分; 各向异性沉积绝缘垫片; 并保形地沉积第二栅电极材料层。

公开(公告)号：US5217924A

公开(公告)日：1993-06-08

申请号：US644855

申请日：1991-01-22

Applicant: Mark S. Rodder ,  Robert H. Havemann

Inventor： Mark S. Rodder ,  Robert H. Havemann

IPC: H01L21/225 ,  H01L21/285

CPC classification number: H01L21/2257 ,  H01L21/2253 ,  H01L21/28518 ,  Y10S148/019

Abstract: A method for forming a shallow junction (56) with a relatively thick metal silicide (52) thereover is provided. A first relatively thin layer (38) of a metal is deposited over the surface of a semiconductor substrate. An impurity (40) is then implanted (42) into or through the first layer (38). A relatively thick second layer (48) of metal is deposited over the first layer (38). An anneal process (50) is then performed to out-diffuse the impurities (40) from the first layer (38) into the substrate (32). The anneal also forms a combined metal silicide (52) from the first layer (38) and the second layer (48). The junction (56) thus formed has less surface damage, reduced spiking and reduced implant straggle than junctions formed according to the prior art. An alternate technique is also disclosed wherein an implant into or through a silicide layer is utilized.

Abstract translation: 提供了一种用于形成其上具有相对厚的金属硅化物（52）的浅结（56）的方法。 第一相对较薄的金属层（38）沉积在半导体衬底的表面上。 然后将杂质（40）（42）注入或穿过第一层（38）。 相对较厚的金属第二层（48）沉积在第一层（38）上。 然后执行退火工艺（50）以将杂质（40）从第一层（38）扩散到衬底（32）中。 退火还形成来自第一层（38）和第二层（48）的组合的金属硅化物（52）。 由此形成的结（56）具有比根据现有技术形成的结更少的表面损伤，减少的尖峰和减少的植入物分裂。 还公开了一种替代技术，其中利用了进入或穿过硅化物层的植入物。

公开(公告)号：US10147793B2

公开(公告)日：2018-12-04

申请号：US14227812

申请日：2014-03-27

Applicant: Borna J. Obradovic ,  Mark S. Rodder ,  Jorge A. Kittl ,  Robert C. Bowen ,  Ryan M. Hatcher

Inventor： Borna J. Obradovic ,  Mark S. Rodder ,  Jorge A. Kittl ,  Robert C. Bowen ,  Ryan M. Hatcher

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth.

公开(公告)号：US09793403B2

公开(公告)日：2017-10-17

申请号：US15054469

申请日：2016-02-26

Applicant: Borna J. Obradovic ,  Robert C. Bowen ,  Titash Rakshit ,  Wei-E Wang ,  Mark S. Rodder

Inventor： Borna J. Obradovic ,  Robert C. Bowen ,  Titash Rakshit ,  Wei-E Wang ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696

Abstract: Multi-layer fin field effect transistor devices and methods of forming the same are provided. The devices may include a fin shaped channel structure on a substrate. The channel structure may include stressor layers stacked on the substrate and a channel layer between the stressor layers, and the stressor layers may include a semiconductor material having a wide bandgap that is sufficient to confine carriers to the channel layer and having a lattice constant different from a lattice constant of the channel layer to induce stress in the channel layer. The devices may also include source/drain regions on respective first opposing sides of the channel structure and a gate on second opposing sides of the channel structure and between the source/drain regions.

公开(公告)号：US09716176B2

公开(公告)日：2017-07-25

申请号：US14534453

申请日：2014-11-06

Applicant: Mark S. Rodder ,  Borna J. Obradovic ,  Robert C. Bowen

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Robert C. Bowen

IPC: H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7848

Abstract: FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, and a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin opposite the first side.

公开(公告)号：US09570609B2

公开(公告)日：2017-02-14

申请号：US14729652

申请日：2015-06-03

Applicant: Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

Inventor： Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L29/786 ,  H01L29/20 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/7845 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.

Abstract translation: 场效应晶体管包括具有应变晶体半导体沟道区的主体层，以及沟道区上的栅叠层。 栅极堆叠包括与沟道区域晶格失配的晶体半导体栅极层，以及栅极层和沟道区域之间的晶体栅极介电层。 还讨论了相关设备和制造方法。

公开(公告)号：US20160322493A1

公开(公告)日：2016-11-03

申请号：US15002078

申请日：2016-01-20

Applicant: Wei-E Wang ,  Mark S. Rodder ,  Ganesh Hedge ,  Christopher Bowen

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Ganesh Hedge ,  Christopher Bowen

IPC: H01L29/78 ,  H01L29/04 ,  H01L21/308 ,  H01L21/764 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/3081 ,  H01L21/764 ,  H01L29/045 ,  H01L29/161

Abstract: Methods of forming a layer of silicon germanium include forming an epitaxial layer of Si1-xGex on a silicon substrate, wherein the epitaxial layer of Si1-xGex has a thickness that is less than a critical thickness, hc, at which threading dislocations form in Si1-xGex on silicon; etching the epitaxial layer of Si1-xGex to form Si1-xGex pillars that define a trench in the epitaxial layer of Si1-xGex, wherein the trench has a height and a width, wherein the trench has an aspect ratio of height to width of at least 1.5; and epitaxially growing a suspended layer of Si1-xGex from upper portions of the Si1-xGex pillars, wherein the suspended layer defines an air gap in the trench beneath the suspended layer of Si1-xGex.

Abstract translation: 形成硅锗层的方法包括在硅衬底上形成Si1-xGex的外延层，其中Si1-xGex的外延层的厚度小于在Si1中形成穿透位错的临界厚度hc -xGex硅; 蚀刻Si1-xGex的外延层以形成在Si1-xGex的外延层中限定沟槽的Si1-xGex柱，其中沟槽具有高度和宽度，其中沟槽具有高度与宽度的纵横比 至少1.5; 并从Si1-xGex柱的上部外延生长Si1-xGex的悬浮层，其中悬浮层在Si1-xGex的悬浮层下方的沟槽中限定气隙。

公开(公告)号：US09461114B2

公开(公告)日：2016-10-04

申请号：US14952152

申请日：2015-11-25

Applicant: Borna J. Obradovic ,  Ryan Hatcher ,  Robert C. Bowen ,  Mark S. Rodder

Inventor： Borna J. Obradovic ,  Ryan Hatcher ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  B82B3/00 ,  H01L29/16

CPC classification number: H01L29/0676 ,  B82B3/0014 ,  B82Y10/00 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/16 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A device may include a nanosheet field effect transistor (FET) that may include a substrate, a well that is doped with impurities at a surface of the substrate, a channel including a plurality of stacked nanosheets, a gate, a conductive material, and an isolation layer. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of the same conductivity type as the impurities of the well. The conductive material may be adjacent the plurality of nanosheets and may electrically connect ones of the plurality of nanosheets to the well. The isolation layer may electrically insulate the well from the workfunction metal.

Abstract translation: 器件可以包括纳米片状场效应晶体管（FET），其可以包括衬底，在衬底的表面上掺杂有杂质的阱，包括多个堆叠的纳米片，沟道，导电材料和 隔离层 多个堆叠的纳米片的一部分可以包括半导体材料，其可掺杂与阱的杂质相同的导电类型的杂质。 导电材料可以与多个纳米片相邻，并且可以将多个纳米片中的一个纳米片电连接到该孔。 隔离层可以将孔与功函数金属电绝缘。