公开(公告)号：US20160204037A1

公开(公告)日：2016-07-14

申请号：US14777736

申请日：2013-06-28

申请人： Niti Goel ,  Ravi Pillarisetty ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Matthew V. Metz ,  Niloy Mukherjee ,  Robert S. Chau

发明人： Niti Goel ,  Ravi Pillarisetty ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Matthew V. Metz ,  Niloy Mukherjee ,  Robert S. Chau

IPC分类号： H01L21/8238 ,  H01L21/762 ,  H01L21/02

CPC分类号： H01L21/823807 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/66795

摘要： Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.

摘要翻译： 通过从在浅沟槽隔离（STI）区域之间形成的第一沟槽的底部的衬底表面外延生长第一类型材料的第一外延区域，形成不同的n型和p型器件鳍。 STI区域和第​​一沟槽高度至少是其宽度的1.5倍。 蚀刻掉STI区域以暴露衬底的顶表面以在第一外延区域之间形成第二沟槽。 在第一外延区域的侧壁上的第二沟槽中形成间隔材料层。 在第二外延区域之间的第二沟槽的底部的衬底表面生长第二类型材料的第二外延区域。 可以从第一和第二外延区域形成正对和p型翅片对。 翅片是共同整合的，并且从材料界面晶格失配减少缺陷。

公开(公告)号：US20140091361A1

公开(公告)日：2014-04-03

申请号：US13631417

申请日：2012-09-28

申请人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

发明人： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

摘要： An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

公开(公告)号：US20130320417A1

公开(公告)日：2013-12-05

申请号：US13997166

申请日：2011-12-27

申请人： Niloy Mukherjee ,  Gilbert Dewey ,  Marko Radosavljevic ,  Niti Goel ,  Sanaz Kabehie ,  Matthew V. Metz ,  Robert S. Chau

发明人： Niloy Mukherjee ,  Gilbert Dewey ,  Marko Radosavljevic ,  Niti Goel ,  Sanaz Kabehie ,  Matthew V. Metz ,  Robert S. Chau

IPC分类号： H01L29/417 ,  H01L29/40

CPC分类号： H01L29/41725 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/26513 ,  H01L21/76814 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66628

摘要： A die includes a semiconductive prominence and a surface-doped structure on the prominence. The surface-doped structure makes contact with contact metallization. The prominence may be a source- or drain contact for a transistor. Processes of making the surface-doped structure include wet- vapor- and implantation techniques, and include annealing techniques to drive in the surface doping to only near-surface depths in the semiconductive prominence.

摘要翻译： 芯片包括半导体突起和突出的表面掺杂结构。 表面掺杂结构与接触金属化接触。 突出可能是晶体管的源极或漏极接触。 制造表面掺杂结构的方法包括湿气和注入技术，并且包括退火技术以在表面掺杂仅在半导体突出中的近表面深度驱动。

公开(公告)号：US20130292698A1

公开(公告)日：2013-11-07

申请号：US13976840

申请日：2011-12-23

申请人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L29/423 ,  H01L29/40

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

公开(公告)号：US20120193609A1

公开(公告)日：2012-08-02

申请号：US13442098

申请日：2012-04-09

申请人： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC分类号： H01L29/66

CPC分类号： H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US20120168877A1

公开(公告)日：2012-07-05

申请号：US12982083

申请日：2010-12-30

申请人： Niloy Mukherjee ,  Gilbert Dewey ,  Marko Radosavljevic ,  Robert S. Chau ,  Matthew V. Metz

发明人： Niloy Mukherjee ,  Gilbert Dewey ,  Marko Radosavljevic ,  Robert S. Chau ,  Matthew V. Metz

IPC分类号： H01L29/78 ,  H01L21/205 ,  H01L21/203

CPC分类号： H01L21/28575 ,  H01L29/66446

摘要： A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.

摘要翻译： 通常使用通过在源极和漏极中使用III-V半导体夹层来降低n沟道晶体管的接触电阻的方法。 在这方面，引入一种器件，其包括具有源极区和漏极区的n型晶体管，与晶体管相邻的第一层间电介质层，穿过第一层间介质层到源极区的沟槽，以及导电源接触 沟槽，源极触点通过III-V半导体夹层与源极区分离。 还公开并要求保护其他实施例。

公开(公告)号：US08193523B2

公开(公告)日：2012-06-05

申请号：US12655468

申请日：2009-12-30

申请人： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC分类号： H01L29/08 ,  H01L29/12

CPC分类号： H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅介电材料允许使用高k值栅极电介质。

公开(公告)号：US20090242873A1

公开(公告)日：2009-10-01

申请号：US12058101

申请日：2008-03-28

申请人： Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Robert S. Chau

IPC分类号： H01L29/12 ,  H01L21/338

CPC分类号： H01L29/7783 ,  H01L29/42316 ,  H01L29/7784

摘要： Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier layer wherein the back gate layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the back gate layer having a first bandgap, a second barrier layer coupled to the back gate layer wherein the second barrier layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the second barrier layer having a second bandgap that is relatively larger than the first bandgap, and a quantum well channel coupled to the second barrier layer, the quantum well channel having a third bandgap that is relatively smaller than the second bandgap.

摘要翻译： 通常描述用于减少短通道效应的半导体异质结构。 在一个示例中，设备包括半导体衬底，耦合到半导体衬底的一个或多个缓冲层，耦合到一个或多个缓冲层的第一势垒层，耦合到第一阻挡层的背栅层，其中背栅层 包括III-V族半导体材料，II-VI族半导体材料或其组合，所述背栅层具有第一带隙，耦合到所述背栅层的第二阻挡层，其中所述第二阻挡层包括III- V族半导体材料，II-VI族半导体材料或其组合，所述第二阻挡层具有相对大于所述第一带隙的第二带隙，以及耦合到所述第二阻挡层的量子阱沟道，所述量子阱沟道具有 相对小于第二带隙的第三带隙。

公开(公告)号：US09099490B2

公开(公告)日：2015-08-04

申请号：US13631534

申请日：2012-09-28

申请人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Niti Goel ,  Sanaz Kabehie ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Niti Goel ,  Sanaz Kabehie ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/423 ,  H01L29/08 ,  H01L29/20

CPC分类号： H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

摘要翻译： 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：US08987091B2

公开(公告)日：2015-03-24

申请号：US13976840

申请日：2011-12-23

申请人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L21/336 ,  H01L31/00 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

摘要翻译： 具有凹入栅极的III-N晶体管。 外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和II​​I-N沟道层之间的III-N蚀刻停止层。 蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。 栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。 蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化​​物的凹陷栅III-N MOS-HEMT。 可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。