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公开(公告)号：US07071014B2
公开(公告)日：2006-07-04
申请号：US10696994
申请日：2003-10-30
CPC分类号： H01L21/02532 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02538 , H01L21/02664 , H01L21/2652 , H01L21/823807 , H01L29/1054
摘要： Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.
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公开(公告)号：US07041170B2
公开(公告)日：2006-05-09
申请号：US10392338
申请日：2003-03-19
申请人： Eugene A. Fitzgerald , Richard Westhoff , Matthew T. Currie , Christopher J. Vineis , Thomas A. Langdo
发明人： Eugene A. Fitzgerald , Richard Westhoff , Matthew T. Currie , Christopher J. Vineis , Thomas A. Langdo
IPC分类号： C30B29/05
CPC分类号： C30B29/52 , C23C16/029 , C23C16/22 , C23C16/4401 , C30B25/02 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262
摘要： A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
摘要翻译： 在半导体材料上沉积梯度的Si 1-x N x N x层的最小化颗粒产生的方法包括在包括Si前体和Ge的气氛中提供衬底 前体，其中所述Ge前体具有大于锗烷的分解温度，以及沉积具有大于约0.15的最终Ge含量的分级的Si 1-x N x Ge x层;以及 衬底上的颗粒密度小于约0.3颗粒/ cm 2。
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公开(公告)号：US06960781B2
公开(公告)日：2005-11-01
申请号：US10794010
申请日：2004-03-05
IPC分类号： H01L20060101 , H01L21/00 , H01L21/26 , H01L21/336 , H01L21/42 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/00 , H01L29/00 , H01L29/06 , H01L29/10 , H01L29/772 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66628 , H01L21/76224 , H01L21/823412 , H01L21/823807 , H01L21/823878 , H01L29/1054 , H01L29/6659 , H01L29/66636 , H01L29/7842 , H01L29/785
摘要： A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor.
摘要翻译： 包括晶体管和沟槽结构的结构，沟槽结构仅在晶体管的沟道区域中仅引起应变的一部分。
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64.发明授权公开(公告)号：US08441055B2
公开(公告)日：2013-05-14
申请号：US13568894
申请日：2012-08-07
IPC分类号： H01L27/108
CPC分类号： H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/10897 , H01L28/40 , H01L29/1054 , H01L29/7849 , H01L29/945
摘要： DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
摘要翻译： 尤其通过将导电材料沉积到沟槽中或掺杂限定沟槽的半导体区域而形成的DRAM沟槽电容器。
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65.发明申请公开(公告)号：US20120302032A1
公开(公告)日：2012-11-29
申请号：US13568894
申请日：2012-08-07
IPC分类号： H01L21/02
CPC分类号： H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/10897 , H01L28/40 , H01L29/1054 , H01L29/7849 , H01L29/945
摘要： DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
摘要翻译： DRAM槽电容器尤其通过将导电材料沉积到沟槽中或掺杂限定沟槽的半导体区域而形成。
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公开(公告)号：US07638842B2
公开(公告)日：2009-12-29
申请号：US11220482
申请日：2005-09-07
IPC分类号： H01L23/62
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/7842 , H01L29/78687 , H01L2924/0002 , H01L2924/00
摘要： Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.
摘要翻译： 通过将形成在其上的替代活性区域材料的图案化衬底接合到刚性电介质平台上，然后与下面的衬底一起去除高缺陷界面区域以产生置于绝缘体上的替代有源区域区域来制造单片晶格失配的半导体异质结构 并且基本上耗尽了错配和穿线位错。
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67.发明授权Solutions for integrated circuit integration of alternative active area materials 有权集成电路集成替代有源区材料的解决方案公开(公告)号：US07626246B2
公开(公告)日：2009-12-01
申请号：US11493365
申请日：2006-07-26
IPC分类号： H01L23/58
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/8258 , H01L27/0605 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming areas of alternative material on crystalline semiconductor substrates, and structures formed thereby. Such areas of alternative material are suitable for use as active areas in MOSFETs or other electronic or opto-electronic devices.
摘要翻译： 在晶体半导体衬底上形成替代材料的区域的方法，以及由此形成的结构。 这种替代材料的领域适合用作MOSFET或其他电子或光电子器件中的有源区域。
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公开(公告)号：US20080265280A1
公开(公告)日：2008-10-30
申请号：US12125308
申请日：2008-05-22
申请人： Matthew T. Currie
发明人： Matthew T. Currie
IPC分类号： H01L27/12 , H01L29/778 , H01L21/336
CPC分类号： H01L29/7849 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L27/1207 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78681 , H01L29/78687
摘要： Abstract Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.
摘要翻译： 摘要半导体绝缘体上的结构有助于器件的制造，包括在工作期间至少部分耗尽的MOSFET，以及包括双层翅片和/或结晶氧化物的FinFET。
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公开(公告)号：US07432139B2
公开(公告)日：2008-10-07
申请号：US11170250
申请日：2005-06-29
申请人： Matthew T. Currie
发明人： Matthew T. Currie
IPC分类号： H01L21/00
CPC分类号： H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02205 , H01L21/0228 , H01L21/26506 , H01L21/3141 , H01L21/3223 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： A method for forming a semiconductor structure, the method including forming in a processing chamber a dielectric layer over a substrate; and subsequently forming, in the same processing chamber and without removing the substrate therefrom, an electrode layer directly over and in contact with the dielectric layer.
摘要翻译： 一种形成半导体结构的方法，所述方法包括在处理室中在衬底上形成电介质层; 并且随后在相同的处理室中形成直接在电介质层上方并与电介质层接触的电极层。
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公开(公告)号：US07335545B2
公开(公告)日：2008-02-26
申请号：US11227529
申请日：2005-09-15
申请人： Matthew T. Currie
发明人： Matthew T. Currie
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/76254 , H01L21/76259 , H01L21/76264 , H01L21/76275 , H01L21/84 , H01L27/1203 , H01L29/66242 , H01L29/66772 , H01L29/66787 , H01L29/66916 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78684 , H01L29/78687 , Y10S438/938
摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance.
摘要翻译： 应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。 受控半导体中的应变被控制以提高器件性能。
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