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1.发明授权Solutions for integrated circuit integration of alternative active area materials 有权集成电路集成替代有源区材料的解决方案公开(公告)号：US07626246B2
公开(公告)日：2009-12-01
申请号：US11493365
申请日：2006-07-26
IPC分类号： H01L23/58
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/8258 , H01L27/0605 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming areas of alternative material on crystalline semiconductor substrates, and structures formed thereby. Such areas of alternative material are suitable for use as active areas in MOSFETs or other electronic or opto-electronic devices.
摘要翻译： 在晶体半导体衬底上形成替代材料的区域的方法，以及由此形成的结构。 这种替代材料的领域适合用作MOSFET或其他电子或光电子器件中的有源区域。
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2.发明申请Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication 有权晶格不匹配的半导体结构具有减少的位错缺陷密度和相关的器件制造方法公开(公告)号：US20110049568A1
公开(公告)日：2011-03-03
申请号：US12845593
申请日：2010-07-28
申请人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
发明人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
IPC分类号： H01L29/06
CPC分类号： H01L21/02609 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/02538 , H01L21/02612 , H01L21/02639 , H01L21/02647 , H01L21/28255 , H01L21/28264 , H01L21/8258 , H01L27/0605 , H01L27/092 , H01L29/04 , H01L29/1054 , H01L29/16 , H01L29/20 , H01L29/66666 , H01L29/66795 , H01L29/778 , H01L29/78 , H01L29/7827 , H01L29/7835 , H01L29/7848 , H01L29/785 , H01L29/78687 , H01L31/028 , H01L31/0304 , H01L31/036 , H01L31/1808 , H01L33/20 , H01L33/30 , H01L33/34 , Y02E10/50
摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
摘要翻译： 具有有限区域的单片晶格失配的半导体异质结构的制造，其具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构的半导体器件的制造。
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3.发明申请Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication 审中-公开具有减少的位错缺陷密度的晶格不匹配的半导体结构和用于器件制造的相关方法公开(公告)号：US20070267722A1
公开(公告)日：2007-11-22
申请号：US11436062
申请日：2006-05-17
申请人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
发明人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
IPC分类号： H01L29/06
CPC分类号： H01L21/8258 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/66666 , H01L29/66795 , H01L29/78 , H01L29/7827 , H01L29/785 , H01L29/78687 , H01L31/1808 , Y02E10/50
摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
摘要翻译： 具有有限区域的单片晶格失配的半导体异质结构的制造，其具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构的半导体器件的制造。
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4.发明授权Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication 有权具有减少的位错缺陷密度的晶格不匹配的半导体结构和用于器件制造的相关方法公开(公告)号：US08324660B2
公开(公告)日：2012-12-04
申请号：US12845593
申请日：2010-07-28
申请人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
发明人： Anthony J. Lochtefeld , Matthew T. Currie , Zhiyuan Cheng , James Fiorenza , Glyn Braithwaite , Thomas A. Langdo
IPC分类号： H01L21/02
CPC分类号： H01L21/02609 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/02538 , H01L21/02612 , H01L21/02639 , H01L21/02647 , H01L21/28255 , H01L21/28264 , H01L21/8258 , H01L27/0605 , H01L27/092 , H01L29/04 , H01L29/1054 , H01L29/16 , H01L29/20 , H01L29/66666 , H01L29/66795 , H01L29/778 , H01L29/78 , H01L29/7827 , H01L29/7835 , H01L29/7848 , H01L29/785 , H01L29/78687 , H01L31/028 , H01L31/0304 , H01L31/036 , H01L31/1808 , H01L33/20 , H01L33/30 , H01L33/34 , Y02E10/50
摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
摘要翻译： 具有有限区域的单片晶格失配的半导体异质结构的制造，其具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构的半导体器件的制造。
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公开(公告)号：US07897493B2
公开(公告)日：2011-03-01
申请号：US11952514
申请日：2007-12-07
CPC分类号： H01L29/66636 , H01L21/02667 , H01L21/26506 , H01L21/324 , H01L29/1054 , H01L29/165 , H01L29/6653 , H01L29/7842 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L29/78687
摘要： Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.
摘要翻译： 在半导体层中诱发应变。 实施例包括通过例如产生自由表面诱导应变。
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6.发明申请Solutions for integrated circuit integration of alternative active area materials 有权集成电路集成替代有源区材料的解决方案公开(公告)号：US20070181977A1
公开(公告)日：2007-08-09
申请号：US11493365
申请日：2006-07-26
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/8258 , H01L27/0605 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming areas of alternative material on crystalline semiconductor substrates, and structures formed thereby. Such areas of alternative material are suitable for use as active areas in MOSFETs or other electronic or opto-electronic devices.
摘要翻译： 在晶体半导体衬底上形成替代材料的区域的方法，以及由此形成的结构。 这种替代材料的领域适合用作MOSFET或其他电子或光电子器件中的有源区域。
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7.发明授权Method for semiconductor sensor structures with reduced dislocation defect densities 有权具有减少位错缺陷密度的半导体传感器结构的方法公开(公告)号：US08809106B2
公开(公告)日：2014-08-19
申请号：US13594519
申请日：2012-08-24
IPC分类号： H01L21/00 , H01L21/02 , H01L31/105
CPC分类号： H01L27/14689 , H01L21/02381 , H01L21/02521 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L27/1446 , H01L27/14612 , H01L27/14643 , H01L31/0304 , H01L31/03046 , H01L31/0312 , H01L31/103 , H01L31/1037 , H01L31/105 , Y02E10/544 , Y02P70/521
摘要： Non-silicon based semiconductor devices are integrated into silicon fabrication processes by using aspect-ratio-trapping materials. Non-silicon light-sensing devices in a least a portion of a crystalline material can output electrons generated by light absorption therein. Exemplary light-sensing devices can have relatively large micron dimensions. As an exemplary application, complementary-metal-oxide-semiconductor photodetectors are formed on a silicon substrate by incorporating an aspect-ratio-trapping technique.
摘要翻译： 非硅基半导体器件通过使用纵横比捕获材料集成到硅制造工艺中。 在结晶材料的至少一部分中的非硅光感测装置可以输出由其中的光吸收产生的电子。 示例性的光感测装置可以具有相对较大的微米尺寸。 作为示例性应用，通过结合纵横比捕获技术在硅衬底上形成互补金属氧化物半导体光电探测器。
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公开(公告)号：US08384196B2
公开(公告)日：2013-02-26
申请号：US13243521
申请日：2011-09-23
申请人： Zhiyuan Cheng , James Fiorenza , Jennifer M. Hydrick , Anthony J. Lochtefeld , Ji-Soo Park , Jie Bai , Jizhong Li
发明人： Zhiyuan Cheng , James Fiorenza , Jennifer M. Hydrick , Anthony J. Lochtefeld , Ji-Soo Park , Jie Bai , Jizhong Li
IPC分类号： H01L29/06
CPC分类号： H01L21/02538 , H01L21/02381 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02543 , H01L21/02546 , H01L21/02636 , H01L21/02639 , H01L21/02647 , H01L29/205 , H01L31/0687 , H01L31/06875 , H01L31/1808 , H01L31/1852 , H01L31/1892 , Y02E10/544
摘要： Methods and structures are provided for formation of devices on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.
摘要翻译： 提供了通过使用纵横比捕获和外延层过度生长来形成衬底上的器件的方法和结构，包括例如晶格失配的材料。 一种方法包括在设置在包括第一半导体材料的基板上的掩模层中形成开口。 在开口内形成包括与第一半导体材料晶格失配的第二半导体材料的第一层。 第一层具有足以在掩模层的顶表面上方延伸的厚度。 包括第二半导体材料的第二层形成在第一层上并且在掩模层的至少一部分之上。 第一层的垂直生长速率大于第一层的横向生长速率，第二层的横向生长速率大于第二层的垂直生长速率。
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公开(公告)号：US08624319B2
公开(公告)日：2014-01-07
申请号：US13013082
申请日：2011-01-25
IPC分类号： H01L27/12
CPC分类号： H01L29/66636 , H01L21/02667 , H01L21/26506 , H01L21/324 , H01L29/1054 , H01L29/165 , H01L29/6653 , H01L29/7842 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L29/78687
摘要： Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.
摘要翻译： 在半导体层中诱发应变。 实施例包括通过例如产生自由表面诱导应变。
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公开(公告)号：US20110114996A1
公开(公告)日：2011-05-19
申请号：US13013082
申请日：2011-01-25
IPC分类号： H01L29/78
CPC分类号： H01L29/66636 , H01L21/02667 , H01L21/26506 , H01L21/324 , H01L29/1054 , H01L29/165 , H01L29/6653 , H01L29/7842 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L29/78687
摘要： Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.
摘要翻译： 在半导体层中诱发应变。 实施例包括通过例如产生自由表面诱导应变。
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