公开(公告)号：US08129821B2

公开(公告)日：2012-03-06

申请号：US10944618

申请日：2004-09-17

申请人： Matthew T. Currie ,  Richard Hammond

发明人： Matthew T. Currie ,  Richard Hammond

IPC分类号： H01L31/117

CPC分类号： H01L29/7848 ,  H01L21/28052 ,  H01L21/2807 ,  H01L21/28255 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/49 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7842

摘要： A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

摘要翻译： 半导体器件和制造半导体器件的方法包括包括第一材料和第二材料的半导体层。 第一和第二种材料可以是硅和锗。 器件的触点具有靠近半导体层的部分和远离半导体层的部分。 远侧部分包括第一材料和第二材料。 与松弛的半导体层相邻并且邻近接触的远端部分形成的金属层与松弛的半导体层和接触的远端部分同时反应以提供金属接触材料。

公开(公告)号：US20110049568A1

公开(公告)日：2011-03-03

申请号：US12845593

申请日：2010-07-28

申请人： Anthony J. Lochtefeld ,  Matthew T. Currie ,  Zhiyuan Cheng ,  James Fiorenza ,  Glyn Braithwaite ,  Thomas A. Langdo

发明人： Anthony J. Lochtefeld ,  Matthew T. Currie ,  Zhiyuan Cheng ,  James Fiorenza ,  Glyn Braithwaite ,  Thomas A. Langdo

IPC分类号： H01L29/06

CPC分类号： H01L21/02609 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78687 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/036 ,  H01L31/1808 ,  H01L33/20 ,  H01L33/30 ,  H01L33/34 ,  Y02E10/50

摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

摘要翻译： 具有有限区域的单片晶格失配的半导体异质结构的制造，其具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构的半导体器件的制造。

公开(公告)号：US07829442B2

公开(公告)日：2010-11-09

申请号：US11941629

申请日：2007-11-16

申请人： Richard Westhoff ,  Vicky K. Yang ,  Matthew T. Currie ,  Christopher Vineis ,  Christopher Leitz

发明人： Richard Westhoff ,  Vicky K. Yang ,  Matthew T. Currie ,  Christopher Vineis ,  Christopher Leitz

IPC分类号： H01L21/20

CPC分类号： H01L21/0251 ,  C30B23/025 ,  C30B23/066 ,  C30B25/02 ,  C30B25/183 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823807

摘要： Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

摘要翻译： 组分梯度半导体层中的位错堆叠被减少或消除，从而导致半导体器件的产量和可制造性的提高。 这是通过在组成渐变层的生长和弛豫期间引入具有多个穿透位错基本上均匀分布在其表面上的半导体层作为起始层和/或至少一个中间层来实现的。 半导体层可以包括接近半导体层的表面并且穿透位错均匀分布在其中的晶种层。

公开(公告)号：US20100206216A1

公开(公告)日：2010-08-19

申请号：US12711560

申请日：2010-02-24

申请人： Eugene A. Fitzgerald ,  Richard Westhoff ,  Matthew T. Currie ,  Christopher J. Vineis ,  Thomas A. Langdo

发明人： Eugene A. Fitzgerald ,  Richard Westhoff ,  Matthew T. Currie ,  Christopher J. Vineis ,  Thomas A. Langdo

IPC分类号： C30B25/00

CPC分类号： C30B29/52 ,  C23C16/029 ,  C23C16/22 ,  C23C16/4401 ,  C30B25/02 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262

摘要： A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.

摘要翻译： 在半导体材料上沉积梯度Si 1-x Ge x层的过程中使颗粒产生最小化的方法包括在包括Si前体和Ge前体的气氛中提供衬底，其中Ge前体具有分解 温度大于锗烷，并沉积具有大于约0.15的最终Ge含量并且小于约0.3颗粒/ cm 2的颗粒密度的梯度Si 1-x Ge 2层在衬底上 。

公开(公告)号：US07776697B2

公开(公告)日：2010-08-17

申请号：US11847721

申请日：2007-08-30

申请人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Richard Hammond ,  Eugene A. Fitzgerald

发明人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Richard Hammond ,  Eugene A. Fitzgerald

IPC分类号： H01L21/00

CPC分类号： H01L29/1054 ,  H01L29/105 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7842 ,  Y10S438/926

摘要： Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

公开(公告)号：US07504704B2

公开(公告)日：2009-03-17

申请号：US11130584

申请日：2005-05-17

申请人： Matthew T. Currie ,  Anthony J. Lochtefeld

发明人： Matthew T. Currie ,  Anthony J. Lochtefeld

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L29/66628 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/785

摘要： A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor.

摘要翻译： 包括晶体管和沟槽结构的结构，沟槽结构仅在晶体管的沟道区域中仅引起应变的一部分。

公开(公告)号：US07326599B2

公开(公告)日：2008-02-05

申请号：US11436281

申请日：2006-05-18

申请人： Anthony J. Lochtefeld ,  Matthew T. Currie

发明人： Anthony J. Lochtefeld ,  Matthew T. Currie

IPC分类号： H01L21/00

CPC分类号： H01L29/7842 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66583 ,  H01L29/78654 ,  Y10S438/938

摘要： In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step.

摘要翻译： 在形成电子器件时，半导体层是预掺杂的，并且在栅极定义之前执行掺杂剂分布退火。 或者，栅极由金属形成。 因此，随后形成的浅源和漏极不受栅极退火步骤的影响。

公开(公告)号：US20070267722A1

公开(公告)日：2007-11-22

申请号：US11436062

申请日：2006-05-17

申请人： Anthony J. Lochtefeld ,  Matthew T. Currie ,  Zhiyuan Cheng ,  James Fiorenza ,  Glyn Braithwaite ,  Thomas A. Langdo

发明人： Anthony J. Lochtefeld ,  Matthew T. Currie ,  Zhiyuan Cheng ,  James Fiorenza ,  Glyn Braithwaite ,  Thomas A. Langdo

IPC分类号： H01L29/06

CPC分类号： H01L21/8258 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78687 ,  H01L31/1808 ,  Y02E10/50

摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

摘要翻译： 具有有限区域的单片晶格失配的半导体异质结构的制造，其具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构的半导体器件的制造。

公开(公告)号：US07202121B2

公开(公告)日：2007-04-10

申请号：US11371687

申请日：2006-03-09

申请人： Matthew T. Currie ,  Anthony J. Lochtefeld

发明人： Matthew T. Currie ,  Anthony J. Lochtefeld

IPC分类号： H01L21/338 ,  H01L21/336 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02532 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02538 ,  H01L21/02664 ,  H01L21/2652 ,  H01L21/823807 ,  H01L29/1054

摘要： Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be formed with little or no consumption of surface silicon. These oxides, such as screening oxide and pad oxide, are formed by deposition onto, rather than reaction with and consumption of the surface layer. Alternatively, oxide deposition is preceded by a thermal oxidation step of short duration, e.g., rapid thermal oxidation. Here, the short thermal oxidation consumes little surface Si, and the Si/oxide interface is of high quality. The oxide may then be thickened to a desired final thickness by deposition. Furthermore, the thin thermal oxide may act as a barrier layer to prevent contamination associated with subsequent oxide deposition.

公开(公告)号：US06891209B2

公开(公告)日：2005-05-10

申请号：US10218007

申请日：2002-08-13

申请人： Mayank Bulsara ,  Matthew T. Currie ,  Anthony J. Lochtefeld

发明人： Mayank Bulsara ,  Matthew T. Currie ,  Anthony J. Lochtefeld

IPC分类号： H01L21/8242 ,  H01L29/94 ,  H01L27/148

CPC分类号： H01L27/10829 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/40 ,  H01L29/1054 ,  H01L29/7849 ,  H01L29/945

摘要： DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.