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96 条记录 (耗时 0.026 秒)

    High voltage low power sensing device for flash memory
    62.
    发明授权
    High voltage low power sensing device for flash memory 有权
    用于闪存的高电压低功率感测装置

    公开(公告)号：US06914821B2

    公开(公告)日：2005-07-05

    申请号：US10696688

    申请日：2003-10-29

    申请人： Tommaso Vali ,  Luca De Santis

    发明人： Tommaso Vali ,  Luca De Santis

    IPC分类号： G11C7/06 ,  G11C16/26 ,  G11C16/28

    CPC分类号： G11C16/26 ,  G11C7/062 ,  G11C7/067

    摘要： Sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-power memory devices using supply potentials that can be significantly higher than the maximum potential to be achieved on a local bit line during a sensing operation. Such sensing devices include an input node selectively coupled to a floating-gate memory cell and an output node for providing an output signal indicative of the programmed state of the floating-gate memory cell. Such sensing devices further include a feedback loop coupled between a precharge path and the input node of the sensing device. The feedback loop limits the potential level achieved at the input node of the sensing device, thus limiting the potential level achieved by the bit lines during sensing.

    摘要翻译： 用于感测浮栅存储器单元的编程状态的感测装置适用于使用能够显着高于在感测操作期间在局部位线上实现的最大电位的电源电位的低功率存储器件。 这样的感测装置包括选择性地耦合到浮动栅极存储器单元的输入节点和用于提供指示浮动栅极存储器单元的编程状态的输出信号的输出节点。 这种感测装置还包括耦合在预充电路径和感测装置的输入节点之间的反馈回路。 反馈环路限制了在感测装置的输入节点处实现的电位电平，从而限制了感测期间由位线实现的电位电平。

    Power down/power-loss memory controller
    64.
    发明授权
    Power down/power-loss memory controller 有权

    公开(公告)号：US10528292B2

    公开(公告)日：2020-01-07

    申请号：US15986804

    申请日：2018-05-22

    申请人： Luca De Santis ,  Tommaso Vali ,  Luca Nubile ,  Ricardo Cardinali ,  Maria L. Gallese ,  Cristina Lattaro

    发明人： Luca De Santis ,  Tommaso Vali ,  Luca Nubile ,  Ricardo Cardinali ,  Maria L. Gallese ,  Cristina Lattaro

    IPC分类号： G11C16/04 ,  G06F3/06 ,  G06F1/26

    摘要： Embodiments of the present disclosure may relate to a memory controller that may include a main controller to begin a power down of a non-volatile memory storage during a first time period, while operating in a first voltage range, wherein the main controller is to begin the power down of the non-volatile memory in response to an indication of a voltage level being below a predetermined threshold; and a sequencer to continue the power down of the memory storage during a second time period, while operating within a second voltage range lower than the first voltage range. In some embodiments, the sequencer may include a state machine to perform a discharge sequence, where the state machine includes a micro-action output to output a micro-action command to the memory storage based at least in part on a current state of the state machine. Other embodiments may be described and/or claimed.

    VOLTAGE SWITCHING IN A MEMORY DEVICE
    67.
    发明申请
    VOLTAGE SWITCHING IN A MEMORY DEVICE 有权
    存储器件中的电压开关

    公开(公告)号：US20120269011A1

    公开(公告)日：2012-10-25

    申请号：US13542250

    申请日：2012-07-05

    申请人： Giulio G. Marotta ,  Carlo Musilli ,  Stefano Perugini ,  Alessandro Torsi ,  Tommaso Vali

    发明人： Giulio G. Marotta ,  Carlo Musilli ,  Stefano Perugini ,  Alessandro Torsi ,  Tommaso Vali

    IPC分类号： G11C5/14 ,  G11C7/00

    CPC分类号： G11C7/12 ,  H03K3/35613 ,  H03K19/018528

    摘要： Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.

    摘要翻译： 公开了电压开关，存储器件，存储器系统和用于切换的方法。 一个这样的电压开关使用串联耦合的一对开关电路，每个开关电路由电平移位电路驱动。 每个开关电路使用具有并联控制晶体管的一组串联耦合晶体管，其中每组中的晶体管数量可由每个晶体管的预期开关输入电压和最大允许电压降确定。 使能信号的特定状态的电压由电平移位电路移动到开关输入电压。 使能信号的特定状态使电压开关导通，使得开关输出电压基本上等于开关输入电压。

    VOLTAGE SWITCHING IN A MEMORY DEVICE
    68.
    发明申请
    VOLTAGE SWITCHING IN A MEMORY DEVICE 有权
    存储器件中的电压开关

    公开(公告)号：US20110273219A1

    公开(公告)日：2011-11-10

    申请号：US12775131

    申请日：2010-05-06

    申请人： Giulio G. Marotta ,  Carlo Musilli ,  Stefano Perugini ,  Alessandro Torsi ,  Tommaso Vali

    发明人： Giulio G. Marotta ,  Carlo Musilli ,  Stefano Perugini ,  Alessandro Torsi ,  Tommaso Vali

    IPC分类号： H03K17/687

    CPC分类号： G11C7/12 ,  H03K3/35613 ,  H03K19/018528

    摘要： Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.

    摘要翻译： 公开了电压开关，存储器件，存储器系统和用于切换的方法。 一个这样的电压开关使用串联耦合的一对开关电路，每个开关电路由电平移位电路驱动。 每个开关电路使用具有并联控制晶体管的一组串联耦合晶体管，其中每组中的晶体管数量可由每个晶体管的预期开关输入电压和最大允许电压降确定。 使能信号的特定状态的电压由电平移位电路移动到开关输入电压。 使能信号的特定状态使电压开关导通，使得开关输出电压基本上等于开关输入电压。

    Sensing scheme for low-voltage flash memory
    69.
    发明授权
    Sensing scheme for low-voltage flash memory 有权
    低压闪存检测方案

    公开(公告)号：US07200041B2

    公开(公告)日：2007-04-03

    申请号：US10932489

    申请日：2004-09-02

    申请人： Giulio G. Marotta ,  Tommaso Vali

    发明人： Giulio G. Marotta ,  Tommaso Vali

    IPC分类号： G11C11/34

    CPC分类号： G11C7/04 ,  G11C7/14 ,  G11C16/24 ,  G11C16/26

    摘要： Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-voltage memory devices. The sensing device has an input node selectively coupled to the memory cell. The sensing device includes a precharging path for applying a precharge potential to the input node of the sensing device for precharging bit lines prior to sensing the programmed state of the memory cell, and a reference current path for applying a reference current to the input node of the sensing device. The sensing device still further includes a sense inverter having an input coupled to the input node of the sensing device and an output for providing an output signal indicative of the programmed state of the memory cell. The reference current is applied to the input node of the sensing device during sensing of the programmed state of the memory cell.

    摘要翻译： 用于感测浮栅存储器单元的编程状态的单端感测装置适用于低电压存储器件。 感测装置具有选择性地耦合到存储单元的输入节点。 感测装置包括用于将预充电电位施加到感测装置的输入节点的预充电路径，用于在感测存储器单元的编程状态之前对位线进行预充电，以及用于将参考电流施加到输入节点的参考电流路径 感测装置。 感测装置还包括感测反相器，其具有耦合到感测装置的输入节点的输入和用于提供指示存储器单元的编程状态的输出信号的输出。 在感测存储器单元的编程状态期间，将参考电流施加到感测装置的输入节点。