公开(公告)号：US20240168879A1

公开(公告)日：2024-05-23

申请号：US18386760

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Kishore K. Muchherla ,  Shyam Sunder Raghunathan ,  Leo Raimondo ,  Jung Sheng Hoei ,  Xiangang Luo ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells each comprising: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is configured to determine a cumulative amount of read disturb stress experienced by the first erase block by monitoring read disturb stress experienced by the first erase block due to: read operations performed on the first erase block; read operations performed on the second erase block; and program verify operations performed on the second erase block. The controller can perform an action on the first erase block responsive to the cumulative amount of read disturb stress experienced by the first erase block meeting a criteria.

公开(公告)号：US11966616B2

公开(公告)日：2024-04-23

申请号：US18175439

申请日：2023-02-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Devin M. Batutis ,  Xiangang Luo ,  Mustafa N. Kaynak ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Sampath Ratnam ,  Shane Nowell

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

Abstract: A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

公开(公告)号：US11934268B2

公开(公告)日：2024-03-19

申请号：US18117555

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Kulachet Tanpairoj

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0649 ,  G06F3/0679 ,  G06F11/076

Abstract: An example apparatus includes a media management superblock component configured to determine that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks; compare the quantity of bad blocks to a bad block criteria; and write host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria. The use of the superblock with a particular quantity of bad block minimizes yield loss for non-use of partial superblocks.

公开(公告)号：US11928356B2

公开(公告)日：2024-03-12

申请号：US17555160

申请日：2021-12-17

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/064

Abstract: Methods, systems, and apparatuses related to source address memory management are described. For example, a controller can be coupled to a memory device to select a source block, a destination block, and a metadata block. The controller can store metadata indicative of an address of the source block in the metadata block. The controller can perform a memory management operation to transfer data from the source block to the destination block.

公开(公告)号：US11823748B2

公开(公告)日：2023-11-21

申请号：US17820792

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Karl Schuh ,  Mustafa N Kaynak ,  Xiangang Luo ,  Shane Nowell ,  Devin Batutis ,  Sivagnanam Parthasarathy ,  Sampath Ratnam ,  Jiangang Wu ,  Peter Feeley

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C7/04 ,  G11C16/32 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C7/04 ,  G11C16/102 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C16/3427

Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.

公开(公告)号：US11740957B2

公开(公告)日：2023-08-29

申请号：US17506505

申请日：2021-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Harish R. Singidi ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Xiangang Luo

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0727 ,  G06F11/0751

Abstract: A failure of a first memory access operation is detected at a memory device. Responsive to the detection, a first error control operation and a second error control operation are performed. In response to a determination that the second error control operation has remedied the failed first memory access operation, the second error control operation is associated with a second priority which is higher than a first priority associated with the first error control operation.

公开(公告)号：US11709727B2

公开(公告)日：2023-07-25

申请号：US17216901

申请日：2021-03-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Sampath K. Ratnam ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Devin M. Batutis ,  Xiangang Luo

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0727 ,  G06F11/0751

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.

公开(公告)号：US11693586B2

公开(公告)日：2023-07-04

申请号：US17357496

申请日：2021-06-24

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246

Abstract: The present disclosure relates to designating or allocating static and dynamic SLC blocks between a non-write burst free block pool and a write burst free block pool. In some embodiments, a free block pool can be utilized by a host for write burst operations and/or non-write burst operations. In these embodiments, the over provisioning portion of the memory sub-system can be designated into a plurality of portions.

公开(公告)号：US11620074B2

公开(公告)日：2023-04-04

申请号：US17203474

申请日：2021-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Devin M. Batutis ,  Xiangang Luo ,  Mustafa N. Kaynak ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Sampath Ratnam ,  Shane Nowell

IPC: G06F3/00 ,  G06F3/06

Abstract: A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.

公开(公告)号：US11609846B2

公开(公告)日：2023-03-21

申请号：US16948302

申请日：2020-09-11

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Karl D. Schuh ,  Jiangang Wu ,  Mustafa N. Kaynak ,  Devin M. Batutis ,  Xiangang Luo

IPC: G11C11/00 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/0882 ,  G11C16/26 ,  G11C16/34 ,  G11C16/10

Abstract: A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device is to perform operations, including receiving a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The operations further include partitioning the set of pages into a set of partitions, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the set of pages is partitioned.